Apparatus for and method of controlling sampling frequency and sampling phase of a sampling device

ABSTRACT

A method of controlling sampling frequency and sampling phase of a sampling device from a value generated by an equalizer coupled to the sampling device includes the steps of generating a complex representation of the value developed by the equalizer and generating a representation of a decision from an output of the equalizer. The complex representation and the decision representation are correlated to obtain a sampling error estimate. The sampling error estimate is used to adjust the sampling frequency and sampling phase of the sampling device.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This 371 application claims the priority benefits of PCT InternationalApplication PCT/US2005/011909, filed Apr. 8, 2005, and claims thebenefit of U.S. Provisional Application No. 60/561,085, filed Apr. 9,2004, and entitled “Advanced Digital Receiver” and further claims thebenefit of U.S. Provisional Application No. 60/601,026, filed Aug. 12,2004, and entitled “Advanced Digital Receiver.” The present applicationalso incorporates by reference U.S. application Ser. No. 10/408,053,filed Apr. 4, 2003, and entitled “Carrier Recovery for DTV Receivers,”U.S. application Ser. No. 09/875,720, filed Jun. 6, 2001, and entitled“Adaptive Equalizer Having a Variable Step Size Influenced by Outputfrom a Trellis Decoder,” (now U.S. Pat. No. 6,829,297), U.S. applicationSer. No. 10/407,634, filed Apr. 4, 2003, and entitled “System and Methodfor Symbol Clock Recovery,” U.S. application Ser. No. 09/884,256, filedJun. 19, 2001, and entitled “Combined Trellis Decoder and DecisionFeedback Equalizer,” and U.S. application Ser. No. 10/407,610, filedApr. 4, 2003, and entitled “Transposed Structure for a Decision FeedbackEqualizer Combined with a Trellis Decoder.”

REFERENCE REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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SEQUENTIAL LISTING

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to digital communicationtechniques, and more particularly, to an apparatus for and method ofadjusting sampling frequency and sampling phase of a sampling device.

2. Description of the Background of the Invention

Discrete data transmission is the transmission of messages from atransmitter to a receiver through a communication channel. A messagesender or sending device, located at the transmitter, communicates witha message receiver by selecting a message and sending a correspondingsignal or waveform that represents this message through thecommunication channel. The receiver determines the message sent byobserving the channel output. Successive transmission of discrete datamessages is known as digital communication. Channel noise ofteninterferes with the transmission and degrades the transmitted messageand leads to some uncertainty as to the content of the original messageat the receiver. The receiver uses a procedure known as detection todecide which message, or sequence of messages, the sender transmitted.Optimum detection minimizes the probability of an erroneous receiverdecision on which message was transmitted.

Messages are comprised of digital sequences of bits converted intoelectrical signals that are sent through the channel. These bits aretypically encoded prior to modulation. Encoding is the process ofconverting the messages from an innate form, typically bits, into valuesthat represent the messages. Modulation is a procedure for convertingthe values into analog signals for transmission through the channel. Thechannel distorts the transmitted signals both deterministically and withrandom noise. Those conditions that interfere with proper receptioninclude additive white Gaussian noise (AWGN) and coherent noise,frequency dependent channel distortion, time dependent channeldistortion, and fading multipath. Because of these effects, there issome probability that the sent message is corrupted when it reaches thereceiver.

Upon reception, the receiver demodulates the incoming waveform. Ingeneral, demodulation attempts to recover the original transmittedsignals as accurately as possible and converts the recovered signals toestimates of the values. There are several steps to this process,including downmixing the radio frequency (RF) and near-basebandintermediate frequency (IF) signals to the baseband representation,channel equalization, and decoding. Symbol and carrier recovery areundertaken so that the discrete time samples are at the correct symbolrate and the signal is moved exactly down to baseband. The receiveremploys a detector to probabilistically determine the value estimates.It is important that the methods of demodulating and detecting thereceived signal as employed by the receiver consider both the possibletransmitted values and potential for channel-induced errors. The valueestimates are then decoded by converting the value estimates back intothe innate form of the message.

Digital communications systems receive the transmitted information byperiodically sampling the output of the demodulator once per symbolinterval. This requires the receiver design to overcome the problemsassociated with system synchronization, as related to symbol timing andcarrier recovery, under non-ideal transmission channel conditions. Theoptimal times for the receiver to sample the received signal aregenerally unknown due to the propagation delay from the transmitter tothe receiver and the influence of channel conditions such as multipath.The propagation delay in the transmitted signal also results in acarrier phase offset. For those transmission systems requiring areceiver to employ a phase-coherent detector, the receiver develops anestimate of the propagation delay and derives an estimate of thetransmitted symbol timing and phase error directly from the receivedsignal. The exception to this is the case where pilot or control signalsare embedded in the transmitted signal. In such a case, the receiveruses the embedded pilot or control signal to synchronize the receiver tothe transmitter. In either case, the receiver overcomes the systemsynchronization obstacles by performing three basic functions: carrierrecovery, timing recovery, and channel equalization.

As noted above, the carrier recovery process includes a number of stepswhereby the received radio frequency (RF) signal is demodulated. Inpart, the near-baseband signal is demodulated so as to recover theinformation-bearing baseband signal and to remove any residual carrierphase offset. This final step is often referred to as phase-locking.

The timing recovery process is used to recover the transmitter time baseand synchronize the receiver and transmitter clocks. Once achieved, thissynchronization permits the receiver to sample the received signal atoptimum points in time and reduce slicing errors.

The channel equalization process attempts to compensate for theimperfections within the transmission channel, which change theamplitude and phase of the received signal as it traverses the channel.These imperfections are generally frequency dependent, time dependent,and dynamic. Because of this, it is advantageous to employ an adaptiveequalizer filter system to remove the amplitude and phase distortionsfrom the channel.

There are a number of phase-locked loop (PLL) techniques in existence. Alimited list of example approaches that will be appreciated by thoseskilled in the art, are Costas loops, squaring loops, and, moregenerally, decision directed and non-decision directed loops.

Phase-locking mechanisms typically involve three common elements. Theyare phase error detection/generation, phase error processing, and localphase reconstruction. The phase error detection operation, asimplemented by a phase detector, derives a phase difference measurementbetween the transmitted signal phase, as detected at the receiver, and aphase estimate of the incoming signal as developed by the receiver. Thephase error measurement is the difference between the phase of thereceived and the actual transmitted signal.

The phase error processing operation, commonly embodied by an integratoror low-pass loop filter, extracts the essential phase difference trendsby averaging, over a period of time or within a time window, themagnitude of the phase error. Properly designed, the phase errorprocessing operation rejects random noise and other undesirablecomponents of the phase error signal. In order to insure stability, theloop filter absorbs gain resident in the phase detector. There areanalog, digital and hybrid analog-digital phase error detection methodsutilized within phase-locked loops. These methods use componentsincluding, but not limited to, modulo-2π phase detectors, binary phasedetectors, phase-splitting filters, and maximum-likelihood carrier phaseestimators.

The local phase reconstruction operation is responsible for controllingthe generation and phase of a local oscillator. The local oscillator isused to demodulate the near-baseband signal with a locally generatedoscillator frequency having the same frequency and phase as thenear-baseband signal. When locked, the resulting local oscillator signalhas the same frequency and phase characteristics as the signal beingdemodulated to baseband. The local oscillator may be implemented usingeither analog or digital means. Various types of voltage controlledcrystal oscillators and numerically controlled oscillators, VCXO's andNCO's, respectively, may be used to regenerate the local carrier.

In the case of an analog circuit, the local phase reconstructionoperation is implemented using a voltage-controlled oscillator. The VCXOuses the processed phase error information to regenerate the local phaseof the incoming signal by forcing the phase error to zero.

Any phase-locking mechanism has some finite delay in practice so thatthe mechanism attempts to predict the incoming phase and then measuresthe accuracy of that prediction in the form of a new phase error. Themore quickly the phase-lock mechanism tracks deviations in phase, themore susceptible the mechanism is to random noise and otherimperfections. This is all the more the case where the received signalexists in a strong multipath environment. Thus, an appropriate trade-offis made between these two competing effects when designing asynchronization system.

Timing recovery, or synchronization, is the process whereby a receiversynchronizes the local time base thereof to the transmitter symbol rate.This allows for precise sampling time instants during the symbol periodso as to maximize the likelihood of correctly determining the value ofthe transmitted symbol. As previously described, the PLL subsystem isinsufficient to recover the symbol rate. Instead, a separatesymbol-timing recovery function is added in combination with the PLL toprovide timing recovery. Improper symbol-timing recovery is one sourceof intersymbol interference (ISI) and significantly degrades theperformance of the receiver.

As those skilled in the art will appreciate, proper sampling of thedemodulator output is directly dependent upon proper timing recovery.There are a number of methods utilized by systems to perform local clockrecovery. In a first system, various types of clocking signals areencoded into the bit stream. In a second system, no predefinedsynchronization symbols are transmitted and only data are sent and thelocked local clock is derived from the received data stream. It shouldbe noted that the latter system appears to be more prevalent due to thedesire for bandwidth efficiency.

In addition, timing recovery methods are also distinguishable as totheir use of the decision device output of the receiver. A non-decisionaided methodology does not depend upon the output of the decisiondevice. An example of such a methodology is the square-law timingrecovery method. Also, envelope-timing recovery is an equivalentsquare-law timing recovery method utilized in a Quadrature AmplitudeModulation (QAM) receiver.

Decision directed (also known as decision-aided) timing recovery usesthe decision device output. One example of a decision directed timingrecovery method minimizes the mean-square error, over the sampling timephase, between the output of either a linear equalizer (LE) or adecision feedback equalizer (DFE) and the decision device output.

The decision device is responsible for assigning a symbol value to eachsample obtained from the demodulator. There are both hard and softdecision devices. An example of a hard decision device is a decisionslicer or a Viterbi decoder. In the case of decision directed timingrecovery methods, care is taken to ensure that there is not excessivedelay between the decision device output and the input samplingfunction. Excessive delay degrades the overall performance of thereceiver or, in the worst-case, causes the phase-locked loop to becomeunstable. As will be appreciated by those skilled in the art, thequality of the symbol-timing estimates is dependent upon the overallsignal-to-noise ratio (SNR) and is a function of the signal pulse shapeand the channel characteristics.

There are numerous sources of channel distortion and interference thatmay result in poor receiver performance, as measured by either bit errorrate (BER) or overall data transfer rates of a receiver design. Factorsinclude noise, AWGN, inter-symbol interference (ISI) and multipathconditions.

Receivers also compensate for channels having significant multipathcharacteristics. There are various means of classifying or describingmultipath phenomenon, depending upon the channel frequency response andtime varying multipath effects. Four common categorizations, familiar tothose skilled in the art, are slow changing frequency non-selectivefading, fast changing frequency-non selective fading, slow changingfrequency selective fading, and fast changing frequency selectivefading.

Typically, multipath is the result of the transmitted signal arriving atthe receiver via different transmission paths, each having a uniquecomposite propagation time to the receiver. The multipath induced ISIresults in the receiver contending with non-constant amplitude andnon-linear phase response of the channel. The second effect is referredto as fading. Fading is due to the propagation delay associated witheach propagation path resulting in constructive and destructiveinterference at the receiver. Fading causes degradation of SNR.

This simplistic description is further refined into four categories,familiar to those skilled in the art, as summarized by the practicalimplications thereof. In practice, a channel exhibiting slowly changing,frequency non-selective fading means that all of the propagation pathsare received within one symbol period and that the channel equallyaffects all the signal frequency components. This is considered the mosteasily compensated fading channel phenomenon. Fast changing, frequencynon-selective fading arises where the channel varies during the symbolperiod. Fast fading is very difficult to compensate effectively.

A channel may be characterized as having slow, frequency-selectivemultipath when the channel distorts the received symbol in the frequencydomain and not all the frequency components are equally affected. As aconsequence, the baseband pulse shape is distorted and intersymbolinterference results. Finally, fast changing, frequency-selective fadingis considered the worst-case type of channel, and results when thereceived symbol is spread over many symbol periods and the channelcharacteristics also vary during the symbol period.

Fading is also roughly divided into large- and small-scale fadingcategories as shown in FIG. 1. Large motions of the receiver, such asoccur in mobile applications, cause large-scale fading, whereassmall-scale fading is due to motion of the receiver. Large-scale fadingis also called log-normal fading, because the amplitude thereof has alog-normal probability density function. Small-scale fading is usuallydescribed as Rayleigh- or Ricean-fading, depending on which probabilitydistribution function (pdf) best describes it. In addition, a Nakagami-mdistribution has also been used to characterize some multipath channelconditions.

Many modern digital communications systems employ adaptive equalizationto compensate for the effects of changing conditions and disturbances inthe signal transmission channel. Equalization is used to remove thebaseband inter-symbol interference caused by transmission channeldistortion and may be performed on baseband or passband signals.Equalization is often performed on the near-baseband signal prior tocarrier recovery and the down mixing to produce a baseband signal. Thisis particularly the case in a decision directed carrier recoveryprocess, as will be appreciated by those skilled in the art, whichrequires at least a partially open eye.

A representation of an 8-VSB, vestigial sideband, eye diagram is shownin FIG. 2. The eye diagram is the overlay of many traces of the receivedRF signal amplitude at the instant of sampling. The convergence of themany signal traces forms seven “eyes” that coincide with the occurrenceof clock pulses in the receiver. At each sampling time, the demodulatedRF amplitude assumes one of eight possible levels. If the 8-VSB signalis corrupted during transmission, these “eyes” will close up anddisappear, as the RF signal will no longer possess the correct amplitudeat the right instant.

An adaptive equalizer filter system is essentially an adaptive digitalfilter having a modifiable frequency and phase response that compensatesfor channel distortions. As will be appreciated by those skilled in theart, several architectures, methods and algorithms are available toimplement this function. In one embodiment, a feed-forward equalizer(FFE) develops a partially equalized signal that is provided to adecision feedback equalizer (DFE). In typical systems of this type, theFFE is responsible for minimizing or eliminating ghosts resulting fromprecursor inter-symbol interference (ISI) while the DFE is responsiblefor minimizing or eliminating ghosts resulting from postcursor ISI. Inanother system, the FFE reduces or eliminates ghosts due to precursorand some postcursor ISI while the DFE reduces or eliminates ghostsresulting from postcursor ISI.

The impact on receiver performance of multipath induced ISI is reducedby the application of channel estimation and equalization. Theeffectiveness of the channel estimate has a direct relationship toelimination of ISI. An ideal channel estimate, in theory, would allowcomplete removal of the ISI. Obtaining an ideal channel estimate,however, is problematic when presented with particularly odious channelcharacteristics.

Another approach to improving performance in the presence of multipathinterference is based on the diversity principle. The differentpropagation paths are used in combination to mitigate the multipathfading. This is possible because the propagation paths are usually notcorrelated, meaning it is unlikely that all of them fade simultaneously.The diversity concept models the channel fading mechanism as a channelburst error. Thus, providing temporally or frequency-based redundantcopies of the transmitted information improves the likelihood ofsuccessful data transmission.

Diversity techniques include temporal diversity and frequency diversity.Frequency diversity requires that the same information be transmittedover a number of carriers where the spacing of successive carriersequals or exceeds the coherent bandwidth of the information channel.Temporal diversity employs the use of a number (L) of independentlyfading versions of the same information-bearing signal transmitted intoL different time slots, where the separation between successive timeslots equals or exceeds the coherence time of the channel. Thus, Lcopies of the transmitted information are presented to the receiver atvarying times based on the transmission path.

One realization of this concept is a Rake Receiver. The Rake Receiverexploits the multipath phenomenon to improve system performance.Multiple baseband correlators are used to individually process multiplemultipath components. The correlator outputs are then added to increasetotal signal strength.

The above characterizations are intended only as a partial, non-limitinglist of example techniques that may be employed and are not intended inany way to represent any limitation upon the disclosed invention.

Despite the numerous techniques available in the present state of theart, receivers exhibit significant performance degradation in thepresence of strong multipath environments. This is particularly true inthe case of terrestrial digital broadcasting systems. In particular, thepresent state of the art receiver using an equalizer typically usessubtractive methods to remove interfering multipath signals. This has adistinct disadvantage in a changing multipath fading environment. Inparticular, these receiver systems attempt to identify and lock onto thesingle strongest received signal coming through a given transmissionpath or channel. This is accomplished at start up of the equalizer byestablishing a tap of unity magnitude at a center point of the FFE. Uponreception, signals corresponding to other transmission paths aresubtractively removed from the incoming total signal. This effectivelyremoves all diversity from the receiving process (if diversity is usedin the system). Also, the receiver can lose lock as the strength of theprimary multipath signal fades or a new stronger signal appears. Thisintroduces significant carrier phase offset at the receiver. Changingmultipath conditions thus often necessitate a receiver to reacquirecarrier lock, resulting in a possibly noticeable disruption ininformation flow to a user at the receiver.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a method of controllingsampling frequency and sampling phase of a sampling device from a valuegenerated by an equalizer coupled to the sampling device includes thesteps of generating a complex representation of the value developed bythe equalizer and generating a representation of a decision from anoutput of the equalizer. The complex representation and the decisionrepresentation are correlated to obtain a sampling error estimate. Thesampling error estimate is used to adjust the sampling frequency andsampling phase of the sampling device.

According to another aspect of the present invention, a decisiondirected control device for controlling sampling frequency and samplingphase of a sampling device from a value generated by an equalizercoupled to the sampling device includes means for generating a complexrepresentation of the value developed by the equalizer and means forgenerating a representation of a decision from an output of theequalizer. The decision directed control device further includes meansfor correlating the decision representation with the complexrepresentation to obtain sampling error estimate and means for adjustingthe sampling frequency and sampling phase of the sampling device usingthe sampling error estimate.

According to yet another aspect of the present invention, acomputer-readable medium for controlling sampling frequency and samplingphase of a sampling device from a value generated by an equalizercoupled to the sampling device includes programming for implementingmultiple routines. A first routine generates a complex representation ofthe value developed by the equalizer and a second routine generates arepresentation of a decision from an output of the equalizer. A thirdroutine correlates the decision representation with the complexrepresentation to obtain a sampling error estimate and a fourth routineadjusts the sampling frequency and sampling phase of the sampling deviceusing the sampling error estimate.

Other aspects and advantages of the present invention will becomeapparent upon consideration of the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing the relationship between small- andlarge-scale fading over time;

FIG. 2 is a graph showing an eight-VSB modulated open eye pattern;

FIG. 3 is a schematic block diagram of an advanced digital receiveraccording to the present invention;

FIG. 4 is a diagram of the ATSC baseband framing code segment formatshowing the data segment and frame sync structure;

FIG. 5 is a schematic of one embodiment of an equalizer for use in theadvanced digital receiver of FIG. 3;

FIG. 6 is a block diagram of one embodiment of a segment sync basedchannel delay estimation unit (CDEU);

FIG. 7 is a diagram showing the relative position of a virtual centerrelative to ghosts detected in a transmission channel;

FIG. 8 is a diagram showing the relative positions of ghosts detected ina transmission channel;

FIG. 9 is a block diagram of one embodiment of an ATSC segment synccorrelator;

FIG. 10 is a block diagram of one embodiment of a “leaky” integrator;

FIG. 11 is a block diagram of one embodiment of a centroid estimator;

FIG. 12 is a flow diagram illustrating operation of a CDEU;

FIG. 13 is a block diagram of another embodiment of a segment sync basedCDEU;

FIG. 14 is a block diagram of an embodiment of a frame sync based CDEU;

FIG. 15 shows the location of ghost signals in a transmission channelrelative to windowing functions;

FIG. 16 is a flow diagram illustrating operation of a further embodimentof a CDEU;

FIG. 17 shows the location of ghost signals in a transmission channelrelative to windowing functions;

FIG. 18 is a block diagram of another embodiment of a frame sync basedCDEU;

FIGS. 19A-19D show the relationship between the virtual center of thevirtual channel, FFE output (Z_(OUT)), and the FFE and DFE taps andcoefficients;

FIGS. 20A and 20B show the relationship between the virtual center ofthe virtual channel, FFE output (Z_(OUT)), and the FFE and DFE taps;

FIG. 21 is a flow diagram illustrating operation of the system 20 ofFIG. 3 for developing an overlapped equalizer structure or an equalizerwithout a fixed center tap;

FIG. 22 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 23 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 24 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 25 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 26 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 27 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 28 is a block diagram of an embodiment of an overlapped equalizerwith a phase tracker;

FIG. 29 is a block diagram of an embodiment of a synchronization anddemodulation feedback system employing an overlapped equalizer;

FIG. 30 is a flow diagram illustrating operation of another embodimentof the system 900 of FIG. 29 for controlling the operation of anoverlapped equalizer optimization process and synchronization anddemodulation control feedback loops;

FIG. 31 is a block diagram of a further embodiment of a synchronizationand demodulation feedback system employing an overlapped equalizer;

FIG. 32 is a block diagram of an embodiment of an overlapped equalizerwithin a combined demodulation and synchronization feedback loop;

FIG. 33 is a block diagram of an embodiment of an overlapped equalizerwithin a combined demodulation and synchronization feedback loop;

FIG. 34 is a block diagram of an embodiment of an overlapped equalizerwithin a combined demodulation and synchronization feedback loop;

FIG. 35 is a block diagram of an embodiment of an overlapped equalizerwithin a combined demodulation and synchronization feedback loop;

FIGS. 36A and 36B show qualitative characteristics of a timing offsetpost filter and carrier offset post filter, respectively;

FIG. 37 is a block diagram of an embodiment of a field/frame synccorrelation directed control system for controlling a VCXO in a digitalreceiver system;

FIGS. 38A-38C show a relationship of a correlation weighting function tolocation of ghost signals in the channel;

FIG. 39 is a block diagram of an embodiment of a correlation directedsynchronization feedback system;

FIG. 40 is a flow chart describing operation of an embodiment of acorrelation directed synchronization feedback loop system;

FIG. 41 is a block diagram of an embodiment of a system producing asegment sync based correlation directed control signal;

FIG. 42 is a flow chart describing operation of an embodiment of asystem for generating a segment sync base correlation directed controlsignal;

FIG. 43 is a block diagram of an embodiment of a segment sync basedcorrelation directed carrier tracking feedback loop; and

FIG. 44 is a block diagram of an embodiment of a channel delay directedsynchronization feedback loop.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

For the purposes of promoting an understanding of the principles of theinvention, reference will now be made to the embodiments illustrated inthe drawings and specific language will be used to describe the same. Itwill nevertheless be understood that no limitation of the scope of theinvention is thereby intended. Any alterations to and furthermodification of the described embodiments, and any further applicationsof the principles of the invention as described herein are contemplatedas would normally occur to one skilled in the art to which the inventionrelates.

One aspect of the present system illustrated in FIG. 3 is a digitalreceiver system with significantly improved stability and performancewhen receiving modulated signals in severe multipath environments. Thetechniques, devices, and systems embodied in this new digital receivermay be adapted to various modulation formats, including, but not limitedto, QAM, offset-QAM and VSB. Illustratively, one non-limiting exampletransmission standard of interest is the ATSC standard adopted for HDTVbroadcast in the United States. The ATSC transmission standard utilizesa suppressed carrier 8-VSB signal having a pilot signal at thesuppressed carrier frequency for use in achieving carrier lock in a VSBreceiver. As shown in FIG. 4, the ATSC data transmission formatcomprises two fields per frame. Each field has 313 segments consistingof 832 multilevel symbols. Each segment has a four symbol segment synccharacter followed by a payload of 828 symbols. The first segment ofeach field contains a field sync segment while the remaining segmentsare used to transport data packets. The field sync is characterized by apredetermined 511 symbol pseudorandom number (PN) sequence and threepredetermined 63-symbol long (PN) sequences. The middle 63-symbol long(PN) sequence is inverted in each successive field. A VSB mode controlsignal (defined in the VSB constellation size) follows the last 63 PNsequence, which is followed by 92 reserved symbols and 12 symbols copiedfrom the previous field. It will be understood by those skilled in theart that the present invention is adaptable to other transmissionstandards without undue experimentation.

One embodiment of the present invention is system 20, shown in FIG. 3.System 20 receives and processes an ATSC broadcast signal and includesan analog front end receiver 30, synchronization 40, digital demodulator42, Nyquist Root Filter (NRF) 44, equalizer 46, forward error correction(FEC) 48, non-coherent control (NCC) 50, decision directed control (DDC)52 and control system 54. Further embodiments of system 20 also detectthe presence of a segment sync, field/frame sync, and thesignal-to-noise ratio, SNR, at various points in system 20.Illustratively, some embodiments of system 20 determine the SNR of thereceived data. Other embodiments determine the SNR of the receivedsignal based on the received synchronization signals. Certain otherembodiments quantify performance of the equalizer based upon the dataerror rate. Similarly, other elements of system 20 also use a data errorrate to quantify the performance thereof. Still other embodiments, alsouse performance metrics developed by the trellis decoder in theequalizer as described in U.S. Pat. No. 6,829,297.

Some embodiments of system 20 also detect a frame or field sync signalin one of the outputs of equalizer 46. Other embodiments of system 20determine whether the synchronization 40 or digital demodulator 42 islocked to the received signal.

The control system 54 connects (not shown) to the various elements ofsystem 20 and generally directs the function of system 20.Illustratively, in some embodiments, control system 54 oversees systemstartup, operational mode selection, and adaptation of equalizercoefficients. As described later, control system 54 receives a channeldelay estimate 84 (CDE), equalizer output 88, and adaptation symboldecision 94. Control system 54 also receives signals segment sync 96,field/frame sync 98, SNR 100, VCXO lock 102, and NCO lock 104. Segmentsync 96 is a signal indicating that a valid segment sync was detected ata desired output of equalizer 46 or other elements of system 20.Field/frame sync 98 is a signal indicating that a valid field/frame syncwas detected at a desired output of equalizer 46 or other elements ofsystem 20. Similarly, SNR 100 is an estimated SNR of the received signalat a desired output of equalizer 46. VCXO lock 102 is a signalindicating that synchronization 40 has locked to the time base of theincoming signal. Finally, NCO lock 104 is a signal indicating thedigital demodulator 42 is locked to the incoming carrier.

The input of analog front end receiver 30 connects to an antenna orother signal source receiving a broadcast signal. The analog front endreceiver 30 tunes to a desired RF broadcast signal, provides automaticgain control (AGC) and signal amplification, and converts the receivedsignal to an intermediate frequency (IF) to be used in the demodulationprocess. The analog front end receiver 30 may include RF tuningcircuits, IF circuitry, and automatic gain control circuitry to optimizethe received signal in the presence of noise. Analog front end receiver30 also down-converts the received signal into a near-baseband signal.Illustratively, the received IF passband signal of a near-basebandcarrier suppressed 8-VSB signal adopted in the ATSC standard may beroughly centered at 5.38 MHz.

In accordance with the present invention, synchronization 40 is part ofthe overall timing recovery function responsible for sampling theincoming signal and synchronizing system 20 to the time base of theincoming signal. Synchronization 40 receives an analog near-basebandsignal 60 from analog front end receiver 30, and produces a digitizednear-baseband signal 62. Synchronization 40 also receives decisiondirected synchronization feedback signal 66 from decision directedcontrol 52, and a non-coherent synchronization feedback signal 64 fromnon-coherent control 54.

In some embodiments of the present invention, the synchronization 40includes an A/D converter (not shown) sampling the incoming analognear-baseband signal 60 to produce a digital near-baseband signal 60based on a sample clock produced by a feedback-controlled VCXO. Controlsystem 54 controls synchronization 40 to select either decision directedsynchronization feedback signal 66 or non-coherent synchronizationfeedback signal 64 to control the phase and frequency of the A/D sampleclock. In other embodiments, synchronization 40 also receives acorrelation directed control feedback signal (not shown). The selectedfeedback signal is filtered to produce a control signal that governs theVCXO output frequency and phase.

Illustratively, in certain embodiments control system 54 initiallyconfigures synchronization 40 to use non-coherent synchronizationfeedback signal 64 to govern the VCXO operation. The analognear-baseband signal 60 is sampled by synchronization 40 based on thefeedback-controlled VCXO sample clock. After system 20 has at leastpartially converged, control system 54 selectively configuressynchronization 40 to use decision directed synchronization feedbacksignal 66 to govern the VCXO operation. Illustratively, some embodimentsof synchronization 40 adapted for an ATSC system include a VCXO drivingA/D sampling at a rate of approximately 21.52 MHz, which is twice thesymbol rate of the received signal in an ATSC system. After the VCXO haslocked to the time base of the received signal, control system 54receives a positive indication from VCXO Lock 102. It will beappreciated that there are numerous techniques available to thoseskilled in the art for determining whether a VCXO is locked to anincoming signal.

In other embodiments, the synchronization 40 re-samples the output of afixed sampling rate A/D. Illustratively, an A/D samples the incomingsignal 60 at a fixed rate. The sample rate converter re-samples thedigitized near-baseband signal to develop a desired output sample ratethat is synchronized to the incoming symbol rate. Similar to thatdiscussed above, control system 54 selectively controls the re-samplingprocess using either non-coherent synchronization feedback signal 64 ordecision directed synchronization feedback signal 66 based on theoperational state of system 20. Digital demodulator 42 is part of theoverall carrier tracking and recovery function of system 20 anddemodulates the near-baseband output of synchronization 40 to baseband.As shown in FIG. 3, the digital demodulator 42 receives the digitizednear-baseband signal 62 from synchronization 40, a decision directedcarrier tracking feedback signal 74 from decision directed control 52,and non-coherent carrier tracking feedback signal 72 from non-coherentcontrol 50. Although not shown, other embodiments of digital demodulator42 also receive a correlation directed control feedback signal.According to one embodiment, the digital demodulator 42 digitally downmodulates the near-baseband signal 62 to a two times over-sampledcomplex baseband output having an in-phase component signal 68 andquadrature component signal 70. Prior to filtering steps, discussedlater, the in-phase component signal 68 and quadrature component signal70 have both negative and positive frequency components. The output ofdigital demodulator 42 is lowpass-filtered by Nyquist Root Filter 44 toremove out-of-band signals.

As explained later, control system 54 selectively controls the feedbacksignal governing the operation of digital demodulator 42. During initialsystem startup, digital demodulator 42 operation is governed by anon-coherent carrier tracking feedback signal from NCC 50. The NCC 50tracks the received carrier frequency and governs the down mix frequencyproduced by a NCO portion of the digital demodulator. After system 20 isat least partially converged, control system 54 configures digitaldemodulator 42 to utilize the decision directed controlled feedback loopsignal to provide improved carrier tracking and governs the downconversion process. At some desired point of digital demodulationoperation, NCO Lock 104 indicates to control system 54 that the NCO islocked to the carrier of the received signal.

In some embodiments of the present invention, only the in-phasecomponent signal 68 is used by the equalizer 46 to reduce the complexityof the system. Alternatively, other embodiments of the present inventionutilize the over-sampled baseband signal in conjunction with afractionally spaced FFE incorporated into equalizer 46 of system 20.

Demodulator 42 provides in-phase component signal 68 and quadraturecomponent signal 70 as inputs to both NRF 44 and NCC 50. NRF 44 filtersout the high frequency components from the demodulated signal to producea filtered in-phase baseband signal (I_(F)) 76 and filtered quadraturebaseband signal (Q_(F)) 78 as inputs to equalizer 46. In someembodiments, NRF 44 is a low-pass filter with a 5.38 MHz double-sidedbandwidth and 11% rolloff.

As described in inventor's co-pending applications, U.S. applicationSer. No. 10/408,053 entitled “Carrier Recovery for DTV Receivers” andU.S. application Ser. No. 10/407,634 entitled “System and Method forSymbol Clock Recovery” herein incorporated, NCC 50 utilizes the pilotsignal and redundant information on the upper and lower Nyquist slopesto develop a non-coherent carrier tracking feedback signal and anon-coherent symbol timing synchronization signal. As mentioned earlier,NCC 50 provides the non-coherent carrier tracking feedback signal 72 asan input to the digital demodulator 42 and the non-coherentsynchronization feedback signal 64 as an input to synchronization 40.

As illustrated in FIG. 3, equalizer 46 receives the baseband componentsignal I_(F) 76 and Q_(F) 78 from the NRF 44. In some embodiments,equalizer 46 utilizes I_(F) 76 and Q_(F) 78. In other embodiments,equalizer 46 only utilizes I_(F) 76, also referred to as the realcomponent of the demodulated signal.

Some embodiments of equalizer 46 establish and update coefficients usingfeed forward techniques, while others use feedback techniques such asLMS fitting. Certain embodiments estimate the channel delay as part ofthis process. Equalizer 46 provides control system 54 with the CDE 84.Control system 54 then directs the equalizer coefficient adaptationprocess through an LMS algorithm to develop a virtual channel responsethat creates a stable received signal by advantageously combining amultiplicity of received ghost signals.

In other embodiments, equalizer 46 includes a trellis decoder integratedinto the equalizer structure. In some embodiments the output of thetrellis decoder is used to update the data samples in the equalizer DFEor direct the equalizer coefficient adaptation process on an ongoingbasis. In other embodiments, intermediate trellis decoder stage outputsare used to direct the equalizer. Still other embodiments, as shown inU.S. patent application Ser. No. 10/407,610, entitled “TransposedStructure for Decision Feedback Equalizer Combined with TrellisDecoder”, include a combined DFE-trellis decoder structure. In yetfurther embodiments, as shown in U.S. patent application Ser. No.09/884,256, outputs from intermediate stages of a trellis encoder arecoupled via a mapper to inputs of certain stages of the DFE.

As described herein, equalizer 46 includes techniques for estimating thechannel delay of the transmission channel through which theinformation-bearing signal is transmitted. Equalizer 46 provides controlsystem 54 with the CDE 84, which is used in conjunction with otherequalizer adaptation techniques to evolve the tap coefficients ofequalizer 46. Control system 54 uses the CDE 84 to align the equalizerrelative to the channel. The CDE 84 is developed from an estimate of thechannel impulse response (CIR). Some embodiments estimate the CIR bycorrelating sync signal arrivals. Certain embodiments use thefield/frame sync signal. Other embodiments use a segment sync signal.Still other embodiments utilize both segment sync and frame sync totrain the coefficients of equalizer 46. In addition, other embodimentsestimate the CIR by correlating other signals within the receivedsignal.

Some embodiments of equalizer 46 have no center tap or reference tap.This advantageously allows the equalizer to remain stable even when amultipath ghost significantly diminishes the main received signal. Otherembodiments include an overlapped equalizer with a virtual centeroutput. In an overlapped equalizer, some samples contained in the FFEand DFE portions of equalizer 46 are temporally related. The overlappedequalizer structure permits the virtual center to be strategicallyplaced within the equalizer to minimize the effect of noise and improveoverall performance. In addition, some embodiments of equalizer 46 alsoinclude a decision directed phase tracker to remove any residual phasenoise not eliminated by the digital demodulator 42. Certain of theseembodiments also include techniques for linking the operation of thedecision directed carrier tracking feedback signal 74 to the operationof the decision directed phase tracker.

As illustrated in FIG. 3, in some embodiments of system 20, equalizer 46provides to decision directed control 52 a synchronization symboldecision 86 and a corresponding equalized data signal 88. As describedherein, the equalized data signal 88 is the data signal provided to thedecision device (not shown) of the equalizer. The synchronization symboldecision 86 is the value produced by a decision device within theequalizer. In some embodiments, the synchronization symbol decision 86is the output of a decision slicer. In other embodiments thesynchronization symbol decision 86 is the output from a selected stageof a trellis decoder. In certain embodiments of the present inventionequalizer 46 provides to decision directed control 52 an intermediateequalized signal 90 corresponding to the synchronization symbol decision86. As described later, in some embodiments intermediate equalizedsignal 90 comes from the output of an FFE. In other embodiments,intermediate equalized signal 90 is the phase-corrected FFE output.

In some embodiments, adaptation symbol decision 94 is a known trainingsignal, such as a generated synchronization signal. In other embodimentsadaptation symbol decision 94 is the output of a decision slicer ofequalizer 46. In certain embodiments, adaptation symbol decision 94 isthe output of a trellis decoder of equalizer 46 or an intermediate stateor other stage of the trellis decoder. In still other embodiments,adaptation symbol decision 94 depends upon the operational state ofsystem 20 or equalizer 46.

Decision directed control 52 generates decision directed carriertracking feedback signal 74 and decision directed synchronizationfeedback signal 66. The decision directed carrier tracking feedbacksignal 74 is a decision weighted carrier tracking error estimate for aparticular received symbol. Similarly, the decision directedsynchronization feedback signal 66 represents a decision weighted timingerror estimate for a received symbol.

The input of FEC 48 receives the FEC symbol decision 80 of equalizer 46.The FEC performs a number of post signal processing steps to correct forerrors contained in the received data. Illustratively, the FEC 48performs frame synchronization, data de-interleaving, and Reed-Solomonforward error correction.

One embodiment of equalizer 46, illustrated as equalizer 200 in FIG. 5,receives as inputs filtered in-phase baseband signal (I_(F)) 76 andfiltered quadrature baseband signal (Q_(F)) 78, and provides as outputsFEC symbol decision 80, synchronization symbol decision 86, equalizeddata signal 88, intermediate equalized signal 90, and adaptation symboldecision 94. As explained herein, some embodiments of equalizer 200 donot process Q_(F).

Equalizer 200 further includes a feedforward equalizer (FFE) 210, adder212, decision device 214, DFE 216, and control system 54. As illustratedin FIG. 5, in some embodiments of equalizer 200, FFE 210 receives as aninput the filtered in-phase baseband signal 76. Although not shown inFIG. 5 for the sake of clarity, some embodiments of FFE 210 also receiveQ_(F). The output of FFE 210 provides intermediate equalized signal 90to the first input of adder 212. The output of DFE 216 provides thesecond input of adder 212. The output of adder 212 is equalized signal88, which serves as the input to decision device 214. Although notshown, control system 54 connects to the various elements of equalizer200, governs the operation of equalizer 200, and adapts the coefficientsof FFE 210 and DFE 216. The FFE is one of a class of filters known inthe art that includes feedforward filters (FFF's) and finite impulseresponse (FIR) filters and it would be apparent to one of ordinary skillin the art to use an FFF or a FIR filter as an appropriate substitutefor the FFE as used herein.

As illustrated in FIG. 5, decision device 214 provides a variety ofoutputs including FEC symbol decision 80, synchronization symboldecision 86, equalizer feedback symbol output 92, and adaptation symboldecision 94. Equalizer feedback symbol output 92 is the decision deviceoutput provided to DFE 216. FEC symbol decision 80 is the final outputof equalizer 200 provided to FEC 48, while synchronization symboldecision 86 is provided to decision directed control 52 (see FIG. 3). Insome embodiments, synchronization symbol decision 86 is the output of adecision slicer circuit. In other embodiments, synchronization symboldecision 86 is obtained from the output or a selected stage of a trellisor Viterbi decoder. In still other embodiments, synchronization symboldecision 86 is selectively obtained from either a decision slicercircuit or the output or state of a trellis decoder depending upon theoperational state of equalizer 200. In the embodiment described herein,synchronization symbol decision 86 may provide different outputs to thecarrier tracking and synchronization feedback loops, respectively.

In some embodiments, equalizer feedback symbol output 92 is obtainedfrom the output of a decision slicer circuit. In other embodiments,equalizer feedback symbol output 92 is obtained from the output or aselected stage of a trellis or Viterbi decoder. In yet otherembodiments, equalizer feedback symbol output 92 updates the values inDFE 216 as they are corrected. Alternatively, control system 54selectively chooses the data source for equalizer feedback symbol output92 depending upon the system operational state.

Control system 54 adapts the coefficients of equalizer 200 usingadaptation symbol decision 94. Similar to synchronization symboldecision 86, in some embodiments, adaptation symbol decision 94 is theoutput of a decision slicer circuit. In other embodiments, adaptationsymbol decision 94 is obtained from the output or a selected stage of atrellis decoder. In yet other embodiments, adaptation symbol decision 94is a training symbol. In still other embodiments, adaptation symboldecision 94 is selectively obtained from the decision device decisionslicer circuit, an intermediate trellis decoder stage, or trellisdecoder output depending upon the operational state of equalizer 200.

In certain embodiments, FEC symbol decision 80, synchronization symboldecision 86, equalizer feedback symbol output 92, and adaptation symboldecision 94 are the same signal from the decision slicer output ofdecision device 214. In certain other embodiments FEC symbol decision80, synchronization symbol decision 86, equalizer feedback symbol output92, and adaptation symbol decision 94 are functionally different and areobtained from different stages of decision device 216 as describedabove.

As a non-limiting example, in some embodiments of the present inventiondecision device 214 is a trellis decoder and selectively controls thesource of the respective outputs. Illustratively, synchronization symboldecision 86 may be selectively obtained from a desired portion of atrellis decoder. In a first instance, control system 54 selectivelycontrols synchronization symbol decision 86 to be a decision sliceroutput of decision device 216. In a second instance, control system 54selectively controls synchronization symbol decision 86 to be apartially or fully error-corrected symbol from the trellis decoder ofdecision device 216.

As shown in FIG. 5, DFE 216 receives as an input equalizer feedbacksymbol output 92. In certain embodiments, for example when decisiondevice 214 includes a trellis decoder, the feedback symbol output 92 isselectively controlled. Illustratively, in certain embodiments of thepresent invention equalizer feedback symbol output 92 may be the outputof a decision slicer portion of a trellis decoder. As the equalizercoefficients are adapted to remove a portion of the transmission channeldistortion, the control system 54 may selectively update the values inDFE 216 from the corrected symbols of the trellis decoder. In certainother embodiments, as described in inventor's co-pending U.S.application Ser. No. 10/407,610 entitled “Transposed Structure for aDecision Feedback Equalizer Combined with a Trellis Decoder,” decisiondevice 214 provides an error-corrected symbol output to DFE 216 from oneof the trace memories of the trellis decoder. In still otherembodiments, as described in inventor's co-pending U.S. application Ser.No. 09/884,256, entitled “Combined Trellis Decoder and Decision FeedbackEqualizer,” the outputs of stages of the trellis decoder are used todevelop inputs to at least a portion of the stages of the DFE.

In the system shown in FIG. 5, control system 54 is connected to FFE210, decision device 214, DFE 216 and CDEU 230, though for clarity notall of the connections are shown. In addition, control system 54receives CDE 84, equalized data signal 88, adaptation symbol decision94, segment sync signal 96 from a segment sync detector (not shown),field/frame sync signal 98 from a field/frame sync detector 218, and SNRsignal 100.

Among other things, control system 54 initializes and controls variousstages and portions of equalizer 200, clock generation, andinitialization and operation of system 20. As described later, controlsystem 54 also develops or adapts filter coefficients of equalizer 200to eliminate the effect of pre-ghost and post-ghost signals.

Equalizer 200 further includes CDEU 230, which includes techniques forestimating the CIR of a transmission channel that is subsequently usedto estimate the channel delay of the transmission channel. In someembodiments, CDEU 230 receives as inputs filtered in-phase basebandsignal, I_(F), 76 and filtered quadrature baseband signal, Q_(F), 78 andprovides the CDE 84 developed from the estimate of the CIR as an outputto control system 54. In certain other embodiments CDEU 230 does notutilize the filtered quadrature baseband signal 78. In still otherembodiments, FFE 210 receives both I_(F) and Q_(F). As can beappreciated by those skilled in the art, the representation of equalizer200 operating on I_(F) is for the sake of simplicity of explanation andnot a limitation.

As described later, CDEU 230 provides the CDE 84 representing thecomposite delay at the input of FFE 210 to control system 54. Asdescribed below, the composite delay reflects the delay associated withthe ghost signals present in the channel. Based on the CDE 84, controlsystem 54 determines the desired temporal location of the segment syncand frame sync signals at the output of equalizer 200 using any of thetechniques described herein. Control system 54 adapts the coefficientsof FFE 210 and DFE 216 based on the difference between equalized datasignal 88 and adaptation symbol decision 94. Some embodiments include anoptional segment sync signal 96 and a field/frame sync signal 98 thatprovides an indication to control system 54 that a field/frame syncsignal 98 was detected (by field/frame sync detector 218). Finally, SNRsignal 100 provides an indication to control system 54 of the relativesignal-to-noise ratio and/or data error rate of the equalized signal atthe output of equalizer 46.

One embodiment of CDEU 230 is shown in FIG. 6. as CDEU 230A, whichestimates the channel delay of the channel by detecting the correlationstrength and relative delay of segment sync sequences of the variousghost signals received at the input of FFE 210 within a segment period.As described in greater detail below, CDEU 230A correlates the receivedsignal for a given symbol time in a segment period with the knownsegment sync sequence. The correlation strengths represent an estimateof the CIR of the transmission channel. The correlation strengths foreach symbol time are then temporally filtered over a sequence of segmentperiods. As will be described in relation to FIG. 7, CDEU 230A thendevelops the CDE 84 by calculating the centroid of the temporallyfiltered correlation strengths within a data segment period relative tothe local time base. Although specific embodiments of CDEU 230 aredescribed with specific hardware and software partitions, this is by wayof example and not limitation. It can be appreciated that otherpartitioning and configuration are contemplated as would normally occurto those skilled in the art.

As a first non-limiting example, illustrated in FIG. 7, system 20receives an ATSC signal transmitted through a channel. The receivedsignal includes a first ghost G₁ and a second ghost G₂. The relativedelay between the arrival of G₁ and G₂ is the estimated delay in arrivalof the segment sync sequence of each ghost at the receiver within asegment period. The strength or magnitude of each ghost is estimatedfrom the correlation strength of the segment sync sequence arriving at aparticular symbol time slot in a segment period. Illustratively, G₁ andG₂ are located at symbol times 128 and 512, respectively, within an 832symbol clock segment period. As shown, the correlation of a segment syncsequence of G₁ is 60% of the magnitude of the correlation of a segmentsync sequence associated with G₂. Applying a weighted average orcentroid calculation, the CDE of the channel is estimated to correspondto symbol time 368.

In a further example illustrated in FIG. 8, the channel of FIG. 7 alsoincludes ghost signals G₃, G₄ and G₅ at data segment symbol times 64,256 and 768, respectively. In some embodiments of the present invention,G₃, G₄ and G₅ are also considered when calculating the CDE. In otherembodiments, a threshold function is applied that filters outconsideration of such smaller-magnitude ghost signals.

Returning to FIG. 6, the CDEU 230A is adapted for operating in thepresence of ghost signals in the transmission channel of a terrestrialATSC broadcast system. CDEU 230A includes correlator 310, integrator312, correlation buffer 314, symbol counter 316, segment counter 318,controller 320, memory 330, and centroid estimator 340. CDEU 230Areceives filtered in-phase baseband signal I_(F) 76 as an input tocorrelator 310. Integrator 312 receives the output of correlator 310 andprovides an output thereof to correlation buffer 314.

Similarly, centroid estimator 340 receives the output of correlationbuffer 314 through interface 342. In the illustrated embodiment,interface 342 is unidirectional, and centroid estimator 340 only readsthe contents of correlation buffer 314. In other embodiments, interface342 is bi-directional, and centroid estimator 340 both reads and writesthe contents of correlation buffer 314.

In some embodiments, symbol counter 316 is a modulo counter thatreceives input from a symbol clock (not shown) and develops a symbolcount output (SC) corresponding to the number of symbols received duringa data segment period. The symbol clock provides a clock edge everysymbol time. Illustratively, an ATSC system segment period consists of832 symbol times. Thus, one embodiment of a symbol counter adapted to anATSC system is a modulo 832 counter with output values from 0 to 831.The symbol count output is incremented each symbol time; however, it isnot necessarily aligned with the segment sync. In addition, someembodiments of symbol counter 316 include a segment indicator output(SI) that is asserted every 832 symbol times. The segment indicatoroutput is timed relative to the first symbol counted by symbol counter316.

One embodiment of segment counter 318 receives the segment indicatoroutput SI of symbol counter 316. Segment counter 318 counts the numberof segment indications produced by the symbol counter and provides asegment count, SEGCNT, corresponding to the number of received segmentindications within a frame time. In still other embodiments, segmentcounter 318 is a modulo 313 counter corresponding to the 313 segmentsper data field in an ATSC transmission. In an alternative embodiment,segment counter 318 receives an input from a symbol clock and incrementsevery 832 symbol times.

Controller 320 includes a first control interface operably connected tocontrol system 54 for communications with other elements of equalizer200 (see FIG. 5), and further may include a second control interface forcommunications with other elements of CDEU 230A, including correlator310, integrator 312, correlation buffer 314, symbol counter 316, segmentcounter 318, memory 330 and centroid estimator 340. The second controlinterface resets the memory and buffer to zero and controls the variouselements of CDEU 230A including, but not limited to, reading and writingconfiguration registers, controlling the reset signal, controllingaccess to memory and register locations, buffer management of thevarious devices and other controls and techniques as may be envisionedby those skilled in the art. Controller 320 also receives the signals SCand SEGCNT from symbol counter 316 and segment counter 318 respectively.

As further illustrated in FIG. 6, some embodiments of CDEU 230A connectcontroller 320 and correlation buffer 314. Correlation buffer 314 hasmemory locations corresponding to the number of symbol times in a datasegment period, denoted herein as array M(i) where i is the index of thearray. The maximum value of i corresponds to the number of symbol timescontained in a data segment. Although not shown, the index variable i isprovided to correlation buffer 314 by controller 320. As explainedherein, in some instances the index variable i has the same value as SCprovided by symbol counter 316. However, in other instances indexvariable i is provided by controller 320 to calculate the CDE 84.

Illustratively, one embodiment of the present invention adapted to theATSC standard includes correlation buffer 314 with 832 memory locationscorresponding to the 832 symbols per data segment. As will beappreciated by those skilled in the art, in certain embodimentscontroller 320 exclusively governs the operation of correlation buffer314. Other embodiments permit integrator 312, controller 320 andcentroid estimator 340 to access correlation buffer 314. Varioustechniques, interfaces, buffer management techniques, memoryorganizations and types are used in various embodiments as would occurto one skilled in the art and all illustrations herein are by way ofexample and are not intended as limitations.

Controller 320 also connects to memory 330 and centroid estimator 340.Other embodiments of CDEU 230A allow control system 54 to access memory330. As shown in FIG. 6, one embodiment of memory 330 includes CDEregister 332, centroid estimate (CENT) register 334, coring thresholdregister 336, and segment count register 338. As explained later indetail, CDE register 332 holds the current estimated delay associatedwith the channel delay measured at the input of FFE 210. CENT register334 contains the centroid estimate generated by centroid estimator 340corresponding to the value stored in CDE register 332. As describedlater, coring threshold register 336 contains a coring thresholdvariable used to filter out or minimize false segment sync detection.Finally, the content of segment count register 338 is the number ofsegments N over which CDEU 230A integrates the correlation valuesproduced by correlator 310 to produce a set of temporally filteredsegment sync correlation values for each symbol time within a segmentperiod. In some alternative embodiments, the values of the coringthreshold and N are static.

Functionally, correlator 310 receives and correlates the four mostrecently received values of I_(F) 76 with a known segment sync sequenceto produce a symbol correlation value, SCV(i). Illustratively, in someembodiments, SCV(i) is the symbol correlation value for the i^(th)symbol time in a data segment and corresponds to the output of symbolcount 316 and the i^(th) array location M(i) in correlation buffer 314.As shown in FIG. 9, one embodiment of correlator 310 is designed for anATSC system, and includes summer 350 and delay line 360. Delay line 360has first, second, third and fourth delay elements (not shown) where thefirst delay element receives I_(F) 76 as an input and has a first delayoutput 362. The second delay element receives first delay output 362 andprovides second delay output 364. The third delay element receivessecond delay output 364 and provides third delay output 366 to thefourth delay element, which, in turn provides fourth delay output 368.The outputs of the first, second, third and fourth delay elementscorrespond to the four most recently received values of I_(F), denotedas I_(F3), I_(F2), I_(F1) and I_(F0), respectively. Summer 350 generatesoutput SCV(i) from inputs I_(F3), I_(F2), I_(F1) and I_(F0). The outputof summer 350 at symbol time i is SCV(i)=I_(F3)−I_(F2)−I_(F1)+I_(F0). Aswill be understood by those skilled in the art, the relatively shortlength of the segment sync sequence, four symbol times, will often leadto noisy correlations SCV(i). Illustratively, data passing throughcorrelator 310 (see FIG. 6) will align itself in a manner to cause amaximum correlation output value. Integrating the values of SCV(i) overa number of segment periods averages out these noisy correlation values.

In one embodiment, integrator 312 is a perfect integrator. In anotherembodiment of integrator 312, integrator 312A as shown in FIG. 10, is a“leaky” integrator and includes data input buffer 370, memory inputbuffer 372, scalar 374, adder 376 and output buffer 378. Integrator 312Areceives SCV(i) at data input buffer 370 from correlator 310 (see FIG.9) corresponding to SC of symbol counter 316. INT(i) is the temporallyaveraged value of SCV(i) obtained by integrating the value of SCV(i)over time and is stored in array M(i) of correlation buffer 314.Integrator 312A receives the previously calculated integration value,denoted as INT_(OLD)(i) for clarity and also corresponding to the symbolcount of symbol counter 316 at memory input buffer 372. It can beunderstood that SCV(i) and INT_(OLD)(i) correspond to the same symboltime within a data segment period. Memory input buffer 372 providesINT_(OLD)(i) to scalar 374. Scalar 374 multiplies INT_(OLD)(i) by thedesired scalar S and provides the product to adder 376. Adder 376 alsoreceives the output of data input buffer 370 and provides the sumINT_(NEW)(i)=SCV(i)+(S·INT_(OLD)(i)) to output buffer 378. Output buffer378 provides INT_(NEW)(i) to correlation buffer 314, which storesINT_(NEW)(i) in M(i).

In some embodiments, where integrator 312A is a perfect integrator, thescalar value is unity (S=1). In those embodiments having a leakyintegrator, the scalar value is less than one. Illustratively, oneembodiment of the present invention uses S=255/256. Integrating thevalues of SCV(i) over a number of segment periods filters out noise inthe received data within correlator 310.

As illustrated in FIG. 11, at least one embodiment of centroid estimator340 includes filter 380, threshold register 382, multiplier 384,subtractor 386, PCDE register 388 and integrator 390. Controller 320(see FIG. 6) reads and writes parameters to threshold register 382 andPCDE register 388. As explained below, integrator 390 provides acentroid error estimate 344 to controller 320. In some embodiments,controller 320 writes the variable threshold, from coring thresholdregister 336 (see FIG. 6) into threshold register 382. In otherembodiments threshold register 382 is equivalent to coring thresholdregister 336. PCDE register 388 contains the proposed channel delayestimate (PCDE) under evaluation. In some embodiments of the presentinvention PCDE register 388 is the equivalent of CDE register 332 (seeFIG. 6).

Controller 320 (FIG. 6) provides the index variable i to centroidestimator 340 of FIG. 11, and the centroid estimator 340 furtherreceives INT(i) from correlation buffer 314 at a first input 342 offilter 380. Filter 380 also includes a second input that receives thevariable threshold from threshold register 382 and provides an output tothe first input of multiplier 384. PCDE register 388 provides thevariable PCDE to the positive input of subtractor 386. The negatinginput of subtractor 388 receives the index variable i from controller320. The output of subtractor 386 is a distance from the PCDE used tocalculate the “moment” (in the mathematical sense) corresponding toINT(i). The output of subtractor 386 is provided as the second input tomultiplier 384, which provides the product to the input of integrator390.

As described below, controller 320 searches for a PCDE value thatminimizes the absolute magnitude of a metric denoted herein asCCE(PCDE). Other embodiments of the present invention look for a changein the sign of CCE(PCDE) to select the CDE without regard to theabsolute magnitude of the CDE. Filter 380 performs the filter functionF(INT(i), threshold) on the absolute value of INT(i) values stored incorrelation buffer 314. Illustratively, in some embodiments, filter 380takes the absolute value of INT(i) and compares it to threshold. Theoutput of filter 380 is F(INT(i), threshold)=0 for those values of|INT(i)|<threshold; filter 380 has an outputF(INT(i),threshold)=|INT(i)| for |INT(i)|>threshold.

In other embodiments, filter 380 compares the squared value of INT(i) tothreshold such that if INT(i)²≧threshold, then the output of the filter380 is equal to INT(i)², otherwise such output is equal to zero. In yetother embodiments, filter 380 has an output F(INT(i),threshold)=|INT(i)|² for |INT(i)|²>threshold. Otherwise, filter 380 hasan output F(INT(i), threshold)=0 for |INT(i)|²≦threshold.

Subtractor 386 develops a sample distance difference (PCDE−i), whichrepresents the delay or number of samples between the proposed CDElocation and the i^(th) sample corresponding to INT(i). Multiplier 384multiplies the sample distance difference signal by the output of filter380. The multiplier product provides an input to integrator 390, whichperforms the summation:

${{CCE}({PCDE})} = {\sum\limits_{i = 0}^{i = 831}{{F\left( {{{INT}(i)},{threshold}} \right)} \times {{Dist}\left( {{PCDE},i} \right)}}}$where CCE(PCDE) is a CIR centroid error estimate and reflects thedistance of PCDE from the position of the centroid of the CIR (i.e., theCDE). Function Dist(x₀, x₁) calculates the number of samples from afirst symbol time, x₀, to a second symbol time, x₁, in a data segment.Illustratively, in some embodiments of ATSC systems Dist(PCDE, i) isdefined to have a negative sign for [(PCDE+416) mod 832]≦i<PCDE and apositive sign for PCDE≦i<(PCDE+416) mod 832.

As a non-limiting example, at least one embodiment of a system adaptedfor an ATSC standard broadcast includes a correlation buffer 314 (seeFIG. 6) with 832 memory locations. Assuming the present value ofPCDE=26,

${{Dist}\left( {{PCDE},i} \right)} = \left\{ \begin{matrix}{d\left( {{PCDE},i} \right)} & {\forall\;{i:{26 \leq i \leq 442}}} \\{- {d\left( {{PCDE},i} \right)}} & {else}\end{matrix} \right.$where d(PCDE, i) is a non-negative distance metric d(x₀,x₁)=|x₀−x₁| and0≦i≦831. It will be appreciated that different boundary conditions andtechniques for calculating a weighted average or centroid estimateappear in various embodiments and can be implemented by those skilled inthe art without undue experimentation. Some alternative embodiments ofthe system include a non-linear distance metric function. In someembodiments the distance metric function d_(K)(x₀,x₁)=|x₀−x₁|^(K).Illustratively, in some embodiments K=2. In other embodiments K is afractional number.

One embodiment of CDEU 230A will now be discussed with continuingreference to elements of FIG. 6, and with reference to the flow chart ofFIG. 12, which illustrates the operation of a system 400 adapted for anATSC broadcast system to estimate the channel delay. At 402,“Initialization,” controller 320 initializes CDEU 230A including, butnot limited to, the contents of correlation buffer 314, symbol counter316, segment counter 318 and integrator 382. In various embodiments thisalso includes the proper initialization of the various controlregisters. In some embodiments, receiving the first three symbol timesof data from filtered in-phase baseband signal I_(F) 76 initializescorrelator 310. After initialization of CDEU 230A, control proceeds to404.

At 404, “SCV,” correlator 310 receives a new symbol from filteredin-phase baseband signal I_(F) 76 and calculates the value of SCV(i)corresponding to the symbol count produced by symbol counter 316.Illustratively, at initial startup correlator 310 produces SCV(0) whereSC=0. System 400 transitions to 406 after calculating SCV(i).

At 406, “Integration,” integrator 312 receives SCV(i) from correlator310 and INT_(OLD)(i) from array M(i) of correlation buffer 314. Atinitial startup each INT(i)=0. Otherwise, INT(i) corresponds to thepreviously stored integration value. Integrator 312 adds SCV(i) to ascaled value of INT_(OLD)(i) to produce INT_(NEW)(i) at output buffer378. Integrator 312 then updates the value of INT(i) stored in arrayM(i) with INT_(NEW)(i). System 400 then proceeds to 410.

At 410, “SC=831,” controller 320 determines whether SC, which is alsothe same as the index variable i, equals the maximum output of symbolcounter output 816. On the condition SC=831 (YES), where the range of SCis 0 to 831, system 400 transitions to 414. Otherwise, on a negativedecision (NO) system 400 transitions to 412. CDEU 230A then incrementssegment counter 316. Upon receiving the new value of SC, controller 320increments the index variable i and transitions system 400 back to 404.

At 414, “SEGCNT<N,” controller 320 compares the output of segmentcounter 318, SEGCNT, to the value N stored in segment count register338. On a positive decision SEGCNT<N (YES), controller 320 branches CDEU230A operation to 416 where segment counter 318 is incremented by one.In addition, the output of symbol counter 315 is set to zero (i.e.,SC=0). However, on a negative decision SEGCNT<N (NO), it has beendetermined that SEGCNT=N, and control passes to 420.

At 420, “Find Initial CDE,” controller 320 searches correlation buffer314 for the location in array M(i) containing the maximum value ofINT(i). The index variable i corresponding to the maximum magnitude ofINT(i) is chosen as the initial value of channel delay estimate (CDE)and placed in CDE register 332 and/or PCDE register 388.

At 422, “CDEU,” centroid estimator 340 calculates the CCE(PCDE) for theproposed CDE value. At 424, “Found CDE,” controller 320 evaluateswhether CCE(PCDE)=0 or SGN(CCE)≠SGN(CENT), where SGN( ) is the signum( )function that returns the sign of the number in the parentheses. Ifeither condition is found to be true, the operation of system 400branches to 432. Otherwise, the operation of system 400 branches to 426.

At 426, “CCE(PCDE)>0,” controller 320 determines whether CCE(PCDE)>0. Ona positive decision (YES), operation of CDEU 230A branches to 430.Otherwise, on a negative decision (NO), CDEU 230A branches to 428. At428, “Increment PCDE,” controller 320A writes the current values of PCDEand CCE(PCDE) into CDE register 332 and CENT register 334, respectively,and increments the value of PCDE stored in PCDE register 388. Theoperation of system 400 then proceeds to 422, and CDEU 230A continuessearching for the CDE.

At 430, “Decrement PCDE,” controller 320A writes the current values ofPCDE and CCE(PCDE) into CDE register 332 and CENT register 334,respectively, and decrements the value of PCDE stored in PCDE register388. The operation of system 400 then returns to 422, and CDEU 230Acontinues searching for the CDE.

At 432, “CCE(PCDE)=0,” controller 320 evaluates whether CCE(PCDE)=0. Ona positive decision (YES), the PCDE value is the desired value and CDEU230A proceeds to 434, where controller 320 writes the value of PCDE intoCDE register 332 and proceeds to Exit. Otherwise, on a negative decision(NO), system 400 proceeds to 436.

At 436, “Select Nearest,” controller 320 determines whetherCENT<CCE(PCDE). On a positive decision, the value stored in CDE register332 is the desired value of the CDE and CDEU 230A proceeds to Exit.Otherwise, the PCDE value is the desired value of the CDE (see 434), andhence, controller 320 writes the value of PCDE register 388 into CDEregister 332. System 400 then proceeds to Exit. Other search algorithmsfor selecting PCDE values are or will become apparent to those skilledin the art for use in this system, and the preceding is not intended asa limitation.

Another embodiment of CDEU 230, as illustrated in FIG. 13, is CDEU 230B,which is adapted for operating in the presence of ghost signals such asexist in a terrestrial ATSC broadcast. CDEU 230B develops an estimatedCDE using both baseband component signals I_(F) 76 and Q_(F) 78 from theNyquist Root Filter 44 (see FIG. 3). The function and operation of CDEU230B is similar to that of CDEU 230A, except that CDEU 230B also usesboth I_(F) 76 and Q_(F) 78 to calculate the correlation of the receivedsignal with the segment sync sequence. CDEU 230B also adds thecorrelation results of the corresponding I_(F) and Q_(F) signals foreach symbol time.

Thus, similar to CDEU 230A, CDEU 230B includes first correlator 310,first integrator 312, first correlation buffer 314, symbol counter 316,segment counter 318, controller 320A, memory 330, and centroid estimator340. In addition, CDEU 230B includes second correlator 310A, secondintegrator 312A, and second correlation buffer 314A. CDEU 230B receivesfiltered baseband signals I_(F) 76 and Q_(F) 78 as inputs to firstcorrelator 310 and second correlator 310A, respectively. Similar tointegrator 312, integrator 312A receives the output of correlator 310A,and SCV_(Q)(i) and INT_(QOLD)(i) from correlation buffer 314A.Integrator 312A provides INT_(QNEW)(i) as an output to correlationbuffer 314. SCV_(Q)(i) is the symbol correlation value for the i^(th)symbol time in a data segment with Q_(F) and corresponds to the outputof symbol counter 316 and the i^(th) array location M_(Q)(i) incorrelation buffer 314A.

Correlator 310, integrator 312 and correlation buffer 314 have similarfunction and operation as previously described in relation to CDEU 230A.Similarly, correlator 310A, integrator 312A, and correlation buffer 314Aare functionally equivalent and perform similar operations and functionsas correlator 310, integrator 312 and correlation buffer 314 in CDEU230A; however, they are adapted to operate on quadrature baseband signalQ_(F) 78. Illustratively, correlation buffer 314 holds the correlationvalues INT_(I)(i) corresponding to I_(F) 76, and correlation buffer 314Aholds the correlation values INT_(Q)(i) corresponding to Q_(F) 78.

The outputs of correlation buffers 314 and 314A provide INT_(I)(i) andINT_(Q)(i), respectively, to the inputs of magnitude calculator 392. Theoutput of magnitude calculator 392 provides MAG(i), a compositemagnitude of INT_(I)(i) and INT_(Q)(i), to centroid estimator 340 andcontroller 320A. Otherwise, controller 320A is functionally andoperationally similar to previously described controller 320. Otherembodiments calculate MAG(i)=INT_(I)(i)²+INT_(Q)(i)². Still otherembodiments calculate MAG(i)=|INT_(I)(i)|+|INT_(Q)(i)|. As will beappreciated, other metrics for the composite magnitude are used in stillother embodiments.

Otherwise, CDEU 230B operates much in the same fashion as CDEU 230A,except that it uses the output of magnitude calculator 392, MAG(i), tocalculate the centroid, whereas CDEU 230A only uses the magnitude ofINT(i). Illustratively, after a sufficient number of segment periods,controller 320A determines the initial position of PCDE by determiningthe value of index variable i corresponding to the maximum magnitude ofMAG(i).

Yet another embodiment of CDEU 230, illustrated in FIG. 14, is CDEU230C, which is also adapted for an ATSC broadcast system. CDEU 230Cestimates the position of the channel delay by detecting the correlationstrength of various received ghost signals with the known frame syncsequence, PN511, within a desired sample window. It will be understoodthat the ATSC frame sync contains a pseudorandom sequence with a cyclicconvolution property. Some embodiments of the present inventionadvantageously calculate the correlation strength of a particular ghostby using a matched filter to take advantage of the relatively longlength of the field/frame sync sequence. Other embodiments develop acorrelation strength estimate by correlating the received signal withthe expected PN511 sequence.

As illustrated in FIG. 15, another non-limiting example transmissionchannel includes ghosts G₁, G₂, G₃ and G₄, each having correlationstrengths above a detection threshold level. The channel also includesghosts G₅, G₆ and G₇, each having correlation strengths below thedetection threshold but above the coring threshold level. Finally, theexample channel has ghosts G₈ and G₉ below the coring threshold level.The relative multipath delay of each ghost is reflected in theirrelative position along the horizontal axis.

Some embodiments of CDEU 230C apply a windowing function to the receivedghost signals. The ghost signals within the window are used to calculatethe channel delay estimate. In some embodiments, the span of the windowis based on the first detected ghost signal that has a frame synccorrelation strength above the detection threshold. As illustrated inFIG. 15, CDEU 230C first detects G₁, with correlation strength above thedetection threshold. CDEU 230C then selects a window span W₁ centeredabout G₁. Those ghosts outside the window are not considered whenestimating the location of the channel delay. It will be appreciatedthat G₄ is not within W₁ and is not considered when estimating thelocation of the channel delay.

Other embodiments of CDEU 230C select a window centered about a ghostwith a maximum or locally maximum correlation strength. As illustratedin FIG. 15, CDEU 230C initially detects G₁ and selects W₁ as the currentwindow, centered about G₁. Subsequently, CDEU 230C detects G₂, with acorrelation strength greater than that of G₁. CDEU 230C then selects anew window, W₂, centered about G₂. As a result, G₇ and G₉ are still notconsidered in the channel delay estimation; however, G₄ is consideredbecause it falls within W₂.

Referring back to FIG. 14, CDEU 230C includes symbol counter 316,segment counter 318, centroid estimator 340A, magnitude calculator 392,correlators 510 and 512, correlation buffer 514, threshold detector 516,controller 520 and memory 530. CDEU 230C receives filtered basebandsignals I_(F) 76 and Q_(F) 78 as inputs to first correlator 510 andsecond correlator 512, respectively. Correlators 510 and 512 provideSCV_(I)(i) and SCV_(Q)(i) to magnitude calculator 392

Correlators 510 and 512 are similar to correlators 310 and 312 of FIG.13, except that they are adapted to provide a correlation between thereceived I_(F) 76 and Q_(F) 78 signals and frame or field sync sequence.SCV_(I)(i) and SCV_(Q)(i) are the correlation strength of the receivedI_(F) 76 and Q_(F) 78 with a frame or field sync sequence. Magnitudecalculator 392 provides MAG_(FS)(i) as an output to threshold detector516 and correlation buffer 514. MAG_(FS)(i) is similar in form andfunction to MAG(i) of FIG. 13, but operates directly on SCV_(I)(i) andSCV_(Q)(i) instead of the integrated values. Correlation buffer 514operably connects to centroid estimator 340A. Controller 520 interfaceswith memory 530 and receives the values of SC and SEGCNT from symbolcounter 316 and segment counter 318, respectively. Similar to controller320 of FIG. 13, controller 520 provides channel delay estimate 84 andhas a first control interface connected to control system 54 (see FIG.3). Controller 520 also has a second interface (not shown for the sakeof simplicity) to the control interfaces of correlator 510, correlator512, correlation buffer 514, threshold detector 516, memory 530, symbolcounter 316, segment counter 318, and centroid estimator 340A.

The second control interface of controller 520 governs the operation ofvarious elements of CDEU 230C including, but not limited to, reading andwriting configuration registers, issuing reset signals, controllingaccess to memory and registers, managing buffers of the various devicesand other functions as will occur to those skilled in the art. Invarious alternative embodiments, the first and second control interfacesof controller 520 include separate data buses, or utilize a single databus, or are each comprised of a plurality of individual data channelsbetween components, as would occur to those of skill in the art.

Finally, memory 530 includes CDE register 332, CENT register 334, coringthreshold register 336, detection threshold register 532 containing thevariable detection threshold T_(DET), window center register 534containing variable WINCENT, frame sync symbol position (FSYM) register536 containing variable FSYM, and frame sync segment position (FSEG)register 538 containing variable FSEG. Some embodiments include windowend register 540 containing variable WINEND and window start register542 containing variable WINSTART.

The detection threshold T_(DET) is the minimum output value of magnitudecalculator 392 that will be deemed to correspond to the detection of aframe sync sequence in the incoming data stream. WINCENT corresponds tothe memory position in correlation buffer 514 that is the center of thewindowing function. FSYM and FSEG are the values of symbol counter 315and segment counter 318, respectively, corresponding to the symbol timethat is located at the center of the windowing function. Finally, thevariables WINSTART and WINEND correspond to the first and last memorylocations of the desired window in correlation buffer 514.

In some embodiments correlation buffer 514 is configured as a circularbuffer having 2n memory locations addressed by index variable i withvalues 0 to 2n−1. In other embodiments correlation buffer 514 holds 2n+1correlation values. As a non-limiting example, for a transmissionchannel with a centroid at WINCENT, WEND=(WINCENT+n) modulo (2n) andWSTART=(WINCENT+n+1) modulo (2n).

Another embodiment of CDEU 230C, illustrated as system 600 that operatesin accordance with the flow chart of FIG. 16, is also adapted for anATSC broadcast. At 602, “Initialization,” the elements of CDEU 230C areinitialized as will be understood by those skilled in the art.Illustratively, with additional reference to FIG. 14, controller 520initializes the registers in memory 530, symbol counter 316, segmentcounter 318, magnitude calculator 392, correlator 510, correlator 512,and correlation buffer 514. Furthermore, index variable i is initializedto zero.

At 604, “Correlation,” correlators 510 and 512 receive the most recentfiltered in-phase and quadrature baseband signals I_(F) 76 and Q_(F) 78,respectively, and perform a correlation on the most recently receivedsequence of bits. As in the embodiment discussed above with reference toFIG. 14, magnitude calculator 392 receives SCV_(I)(i) and SCV_(Q)(i)from correlators 510 and 512, respectively, and calculates the magnitudeof the correlation, MAG_(FS)(i). MAG_(FS)(i) is provided as an output tocorrelation buffer 514 and threshold detector 516. Correlation buffer514 stores MAG_(FS)(i) in array M(i). System 600 then proceeds to 606.

At 606, “Detect Frame Sync,” if MAG_(FS)(i)≧T_(DET) (YES) a positiveindication is sent to controller 520. System 600 then branches to 610.Otherwise, threshold detector 516 sends a negative indication (NO) (noframe sync detected) to controller 520. System 600 then branches to 612.In some embodiments, controller 520 branches CDEU 230C operation to 610only upon detection of the first frame sync. Similar to window W₁ ofFIG. 15, this results in the window function being centered about thefirst ghost signal with a frame sync correlation above T_(DET).

In other embodiments, at 606, controller 520 branches CDEU 230Coperation to 610 when any frame sync is detected or MAG(i)>CENT.Illustratively, the CENT register is initialized with CENT=T_(DET). Afirst positive indication (YES) is sent to controller 520 whenMAG_(FS)(i)≧T_(DET). On each positive indication, controller 520 setsCENT=MAG_(FS)(i). Additional positive indications are generated whenMAG_(FS)(i)≧CENT. This results, similar to window W₂ of FIG. 16, in thewindow function being centered about the ghost signal with the maximumframe sync correlation. Otherwise, controller 520 branches CDEU 230Coperation and system 600 proceeds to 612.

At 610, “Store Center,” controller 520 sets FSYM=SC and FSEG=SEGCNT,where FSYM and FSEG represent the location of detected frame sync withinthe data packet field/frame structure. Controller 520 sets CDE=i as theinitial estimate of the channel delay. In some embodiments, controller520 also sets CENT=MAG(i) as the magnitude of the correlationcorresponding to the initial channel delay estimation. The controller520 also calculates the location WINEND. System 600 then proceeds to612.

At 612, “Continue,” controller 520 branches operation of CDEU 230C independence upon whether WINEND has been reached. On the negativeindication (NO), CDEU 230E has not previously detected a frame sync orCDEU 230E has detected a previous frame sync but i≠WINEND. In thisevent, system 600 branches operation to 614. Otherwise, controller 520has determined that WINEND has been reached and branches operation to615 FIND CDE. As described below, system 600 determines the CDE of thechannel at FIND CDE.

At 614, the values of symbol counter 316 and segment counter 318 areupdated. Index variable i is also incremented. System 600 returns to604.

Some embodiments of CDEU 230C include centroid estimator 340A thatestimates the delay of a channel by calculating the weighted average, orcentroid, of the correlation values within the windowing function. Aswill be understood by those skilled in the art, centroid estimator 340Ais operationally and structurally similar to centroid estimator 340,except that centroid calculator 340A is adapted to operate on the valuesof MAG_(FS)(i) stored in correlation buffer 514. Correlation buffer 514and controller 520 of centroid estimator 340A interface and operateequivalently or in much the same fashion as correlation buffer 314 andcontroller 320 in centroid estimator 340. Thus, similar to centroidestimator 340, centroid estimator 340A performs the summation:

${{CCE}({PCDE})} = {\sum\limits_{WINDOW}{{F\left( {{{MAG}(i)},{threshold}}\; \right)} \times {{Dist}\left( {{PCDE},i} \right)}}}$over the values contained in the desired WINDOW of memory locations incorrelation buffer 514. Similar to controllers 320 and 320A ofpreviously described embodiments of CDEU 230, controller 520 interactswith centroid estimator 340A (not shown) and correlation buffer 514 todetermine the location of the correlation value that corresponds to thedelay of the channel.

Other embodiments of CDEU 230C determine the delay of a channel bycalculating the weighted average or centroid of the correlation valuesof a subset of the correlation values within the windowing function. Asillustrated in FIG. 17, in some embodiments, controller 520 divides thewindow into regions centered around the ghost signal with the maximumcorrelation value G_(MAX) corresponding to sample i=I_(MAX), such thatM(I_(MAX))=G_(MAX) within the window. In other embodiments, region R₀has some width about I_(MAX). Region R₁ is the portion of the windowfrom WINSTART to region R₀ and contains pre-ghost signals relative toI_(MAX). Region R₂ is the portion of the window from region R₀ to WINENDand contains post-ghost signals relative to I_(MAX).

Illustratively, initially controller 520 searches correlation buffer 514to locate G_(MAX). Controller 520 then searches region R₁ to locate thepre-ghost signal G_(PRE) (corresponding to i=I_(PRE), such thatM(I_(PRE))=G_(PRE)) and post-ghost signal G_(POST) (corresponding toi=I_(POST), such that M(I_(POST))=G_(POST)) closest to I_(MAX). In someembodiments, controller 520 only considers those ghost signals withMAG_(FS)(i)>T_(DET). As shown in FIG. 15, G₂ is G_(MAX), G₁ is G_(PRE),and G₃ is G_(POST).

Similar to controller 320 in CDEU 230A, controller 520 determines thelocation of PCDE by evaluating the equation:CCE(PCDE)=G _(MAX) ·Dist(PCDE,I _(MAX))+G _(PRE) ·Dist(PCDE,I _(PRE))+G_(POST) ·Dist(PCDE,I _(POST))where Dist(PCDE, i) is defined as negative for values of i lying betweenWINSTART and CDE, and positive for values of i lying between CDE andWINEND. In still other embodiments, controller 520 first considers ghostsignals with MAG_(FS)(i)>T_(DET); however, ghost signals above thresholdare also considered. By way of a non-limiting example, one embodiment ofsystem 20 adapted for an ATSC standard broadcast has a correlationbuffer 514 containing 1024 samples with a window width of 1024 samples.Under one possible channel condition, FSYM=128, WINSTART=640 andWINEND=639. Given PCDE=26:

${{Dist}\left( {{PCDE},i} \right)} = \left\{ \begin{matrix}{d\left( {{PCDE},i} \right)} & {\forall\;{i:{26 \leq i \leq 640}}} \\{- {d\left( {{PCDE},i} \right)}} & {else}\end{matrix} \right.$where d(PCDE, i) is a non-negative distance metric d(x₀,x₁)=|x₀−x₁| and0≦i≦1023.

Different boundary conditions and techniques for calculating a weightedaverage or centroid estimate can be applied to this system without undueexperimentation. In some embodiments, controller 520 selects the valueof CDE that minimizes the absolute magnitude of CCE(PCDE). In otherembodiments, controller 520 selects the value of CDE where the sign ofCCE(PCDE) changes.

Still another embodiment of CDEU 230, illustrated in FIG. 18, is CDEU230D, which is also adapted for an ATSC broadcast system, and estimatesthe delay of the channel by detecting the correlation strength ofvarious received ghost signals with the frame sync sequence, PN511,within a desired sample window. CDEU 230D is similar in form andfunction to CDEU 230C except that it only operates only on the filteredin-phase baseband signal I_(F) 76, whereas CDEU 230C uses both I_(F) 76and Q_(F) 78. Thus, correlator 510 provides SCV_(I)(i) to correlationbuffer 514 and threshold detector 516. Since CDEU 230D does not includeSCV_(Q)(i), there is no need to calculate MAG_(FS)(i). As will beunderstood by those skilled in the art, CDEU 230D is adapted to estimatethe delay of the channel based on the magnitude of the frame sync withI_(F), whereas CDEU 230C uses both I_(F) and Q_(F). Thus, correlationbuffer 514 stores M(i)=SCV_(I)(i). CDEU 230D functions similarly to CDEU230C, except that CDEU 230D uses SCV_(I)(i) in place of MAG_(FS)(i).Thus:

${{CCE}({PCDE})} = {\sum\limits_{WINDOW}{{{F\left( {{{SCV}_{I}(i)},{threshold}}\; \right)} \times {{Dist}\left( {{PCDE},i} \right)}}.}}$

Similar to before, filter 380 compares either the square or absolutevalue of SCV_(I)(i) to the value of threshold and provides an outputF(SCV_(I)(i),threshold)=|SCV_(I)(i)| for |SCV_(I)(i)|>threshold.Otherwise, filter 380 has an output F(SCV_(I)(i),threshold)=0 for|SCV_(I)(i)|≦threshold.

Alternatively, other embodiments of filter 380 filters SCV_(I)(i) basedupon the SCV_(I) ²(i)>threshold and provides an outputF(SCV_(I)(i),threshold)=|SCV_(I)(i)|² for |SCV_(I)(i)|²>threshold.Otherwise, filter 380 has an output F(SCV_(I)(i),threshold)=0 for|SCV_(I)(i)|²≦threshold.

After the delay of the channel is estimated, the values of FSEG and FSYMare adjusted to reflect the location of the correlation valuecorresponding to the delay of the channel. FSYM and FSEG are the valuesof symbol counter 315 (SC) and segment counter 318 (SEGCNT),respectively, corresponding to the symbol time that is located at thecenter of the windowing function. In some embodiments, controller 520estimates the delay of the channel by searching for a PCDE value thatminimizes the absolute magnitude of CCE. In other embodiments,controller 520 estimates the channel delay by searching for the PCDEvalue that causes a change in the sign of CCE(PCDE). Controller 520increments PCDE until the sign of CCE(PCDE) changes. Controller 520 thenselects the current PCDE value as the CDE value without regard to theabsolute magnitude of CCE(PCDE).

Returning to FIG. 5, during normal operation, equalizer system 200compensates for the channel intersymbol interference distortion byperforming a filtering operation on the received signal. FFE 210receives filtered in-phase baseband signal I_(F) 76 as an input. Theadder 212 sums the outputs of DFE 216 and FFE 210 to produce equalizeddata signal 88. Decision device 214 samples equalized data signal 88 andestimates the received symbol.

Initially, control system 54 adapts the coefficients of FFE to remove aportion of the associated channel distortion, and DFE 216 is disabled.After some period of time, the coefficients of FFE 210 are adaptedsufficiently to remove a portion of the channel-related distortion andnoise, which will allow the DFE to operate effectively. Followinginitial startup, DFE 216 is enabled and the coefficients of FFE 210 andDFE 216 are adapted using various techniques as would occur to one ofordinary skill in the art to remove the remaining portion of the channeldistortion, such as LMS adaptation. The decision device 214 samplesequalized data signal 88 to obtain a symbol-level representation of thereceived signal at the output of a decision slicer.

Decision device 214 provides equalizer feedback symbol output 92 to DFE216 as an input. In some embodiments, for example, the decision device214 is a decision slicer, and equalizer feedback symbol output 92 is theoutput of the decision slicer. In other embodiments, the decision device214 corrects received symbol errors. In other embodiments of equalizer200, wherein the decision device 214 includes a trellis decoder,equalizer feedback symbol output 92 may be selectively controlled.During initial system start equalizer feedback symbol output 92 is anuncorrected symbol output from decision device 214. In some embodimentsincluding a decision device with a trellis decoder, the equalizercontrol system 54 may selectively control equalizer feedback symboloutput 92 to provide the output of the trellis decoder or a stage in thetrace memories of the trellis decoder. In still other embodiments, asshown in inventor's co-pending U.S. patent application Ser. Nos.09/884,256 entitled “Combined Trellis Decoder and Decision FeedbackEqualizer” and, 10/407,610 entitled “Transposed Structure for a DecisionFeedback Equalizer Combined with a Trellis Decoder,” the decision device214 continuously updates the recovered symbol values used by the DFE asthey are corrected by the trellis decoder. Additionally, in someembodiments, equalizer 200 is adapted as either a real or complex filterso as to be compatible with various modulation techniques.

Certain embodiments develop equalizer coefficients in a manner such thatthere is not a predefined or fixed center tap. Instead, the FFE outputhas a virtual center that does not correspond to a specific filter tapor combination of taps and all of the taps of the FFE are dynamicallydetermined. The virtual center position is based on an estimate of thetransmission channel delay.

As illustrated in FIG. 19A, with reference to certain items in FIG. 5,one non-limiting example of a possible channel condition (depicted bythe channel impulse response 711) has two equal strength ghost signals710 and a virtual center 712 of the virtual channel. Equalizer 200provides control system 54 a channel delay estimate that is an estimateof the delay of the channel present at the input of FFE 210 relative tothe local time of system 20. Control system 54 uses the channel delayestimate to calculate an offset position for a generated training symbolsequence (e.g., a segment or frame sync sequence) by adding the channeldelay measured at the FFE to the desired delay of the equalizer output.As described herein, control system 54 compares the received signal tothe generated training signal. In some embodiments the training signalis a segment sync sequence. In other embodiments the generated trainingsignal is a field/frame sync sequence or a combination of othersynchronization signals expected in the received signal. In still otherembodiments, control system 54 initially generates a segment syncsequence. After the equalizer has at least partially converged, controlsystem 54 generates a frame/field sequence. Control system 54 adapts theequalizer coefficients to align the synchronization signals of thereceived signals with the desired temporal location as referenced by thegenerated synchronization signals. Illustratively, in some embodiments,system 20 aligns the output of equalizer 200 with a particular FFE tapand thereby adapts the equalizer to a particular channel condition.

As illustrated in FIG. 20A, as a non-limiting example described withcontinuing reference to FIG. 5, one embodiment of equalizer 200 includesa FFE 210 with 1024 FFE taps and DFE 216 with 512 DFE taps. Theindividual taps of the DFE are referenced by a tap index. Control system54 aligns the equalizer such that the output of equalizer 200 istemporally aligned with the 768^(th) tap of the FFE 210. Moving thevirtual center 712 to a later point in time improves the performance ofthe equalizer with respect to pre-ghost signals. As another non-limitingexample, shown in FIG. 20B, one embodiment of the same system includescontrol system 54 aligning the equalizer 200 with the 512^(th) tap ofFFE 210 such that the FFE works equally well on pre-ghost and post-ghostcomponents in the channel.

Referring back to FIG. 19B with continuing reference to FIG. 5, FFE 210is initially adapted to develop an output centered about the desiredvirtual center location 712, corresponding to FFE tap Z_(OUT), based onthe location of various synchronous signals within the received signal.Some embodiments of a system 20 are adapted to operate on an ATSC systemand train the equalizer based upon the expected arrival time(SEGMENT_SYNC_OUT) of a segment sync signal. Control system 54 generatesa segment sync signal as a training sequence when SC=SEGMENT_SYNC_OUT.The received signal is compared to the generated training sequence todevelop an error signal used to adapt the coefficients of equalizer 200.Still other embodiments train the coefficients of equalizer 200 based onthe expected arrival time (FRAME_SYNC_OUT) of an ATSC frame or fieldsync. Thus, similar to before, control system 54 generates a frame syncsignal as a training sequence when SEGCNT=FRAME_SYNC_OUT. The receivedsignal is compared to the generated frame sync training sequence todevelop an error signal used to adapt the coefficients of equalizer 200.Still other embodiments of system 20 adapt the coefficients of equalizer200 using both the frame sync and segment sync.

Illustratively, given a desired equalizer output location, Z_(OUT),control system 54 positions the relative expected timing of a trainingsignal derived from an ATSC segment sync at symbol counter timeSEGMENT_SYNC_OUT=(Z_(OUT)+CDE) mod 832. Similarly, control system 54calculates the value of the symbol counter 316 and segment counter 318to position the relative timing of a training signal derived from anATSC frame/field sync. Control system 54 causes the frame/field syncbased training signal to occur when symbol counter 316 output SC equalsSEGMENT_SYNC_OUT=(Z_(OUT)+CDE) mod 832 and segment counter 318 outputSEGCNT equals FRAME_SYNC_OUT=FSEG mod 313 segment times. By way ofexample, one embodiment of system 20 adapted for an ATSC standardbroadcast has a 1024-sample-long correlation buffer 514 and uses bothfield/frame sync and segment sync to adapt the coefficients of equalizer200. Assuming the desired output delay in FFE 210 is Z_(OUT)=768 withCDE=800 and FSEG=312, control system 54 calculates SEGMENT_SYNC_OUT=736and FRAME_SYNC_OUT=312.

Additionally, in some embodiments of system 20, control system 54 adaptsthe filter coefficients of equalizer 200 over time to create the virtualcenter (representing the delay of the FFE 210) that moves in response tochanging channel conditions. The equalizer constructs the virtualchannel or signal composed of several signal transmission paths or ghostsignals and is not necessarily aligned with one ghost signal. Thus, thestability of equalizer 200 is not dependent upon a single main ghostsignal. This provides additional robustness in that the addition ordeletion of any one multipath contributory signal does not cause theequalizer to become unstable or otherwise necessitate re-initializationor re-acquisition of the signal.

As illustrated in FIG. 19B, in some embodiments of equalizer 200, FFE210 and DFE 216 operate in an overlapped region where a portion of thesamples in the FFE 210 and DFE 216 are temporally related. Somealternative embodiments of equalizer 200 include a fractionally spacedFFE. In any event, the samples in FFE 210 and DFE 216 are temporallyrelated but not necessarily temporally aligned to the same samplespacing. In other embodiments of equalizer 200, as shown in FIG. 19C,some embodiments of equalizer 200 include an overlapped region where allthe samples in DFE 216 are temporally related to samples in FFE 210.

A shown in FIG. 19B, some embodiments control the equalizer operationwhereby the coefficients of equalizer 200 are initially set to apredetermined value and the coefficients of FFE 210 are adapted toremove some portion of the channel distortion. Once the equalizerreaches a desired state of performance, the coefficients of DFE 216 arefreely adapted. As illustrated in FIG. 19C, the coefficients of DFE 216begin to grow, which typically yields decreases in the magnitudes of oneor more of the coefficients of FFE 210. In some embodiments, as shown inFIG. 19D, the coefficients of DFE 216 grow as the coefficients of FFE210 in the overlapped region tend towards zero magnitude. However, inother embodiments, the coefficients in FFE 210 have some remainingmagnitude in the overlapped region. As will be understood by thoseskilled in the art, this operation automatically occurs as a result ofthe design of equalizer 200 and allows control system 54 to balance thenoise and ghost performance of equalizer 200.

Control system 54 uses a variety of error evaluation techniques, asknown by those skilled in the art, to adapt the equalizer coefficientsto further remove the channel distortion. Illustratively, certainembodiments use a Reduced Constellation Algorithm (RCA) errorcalculation in combination with an LMS algorithm to adapt the equalizercoefficients. The RCA-LMS algorithm detects channel equalization errorand evolves an improved equalizer response over time. Other embodimentsuse a data directed technique in combination with an LMS algorithm toadapt the equalizer coefficients. Still other embodiments use otherblind equalization techniques for adapting the coefficients of theequalizer 200. Illustratively, some embodiments use a constant modulusalgorithm (CMA) for blindly adapting the equalizer coefficients.

As described in greater detail hereinafter, control system 54 initiallyadapts (i.e., determines) the FFE coefficients. Once the FFE 210 of theequalizer 200 is operating, the system enables DFE 216 and furtheradapts the equalizer coefficients to remove any residual channeldistortion and respond to changes in channel conditions. All of the DFEcoefficients are initially set to zero and at least a portion of thecoefficients of the DFE 216 evolve to non-zero values.

In other embodiments, FFE 210 uses fractionally spaced samples, and thesystem includes a technique for sub-sampling or sample rate convertingthe FFE output to provide proper temporally aligned data to the decisiondevice 216. Illustratively, in some embodiments the sample rateconversion process occurs at the FFE output. In certain embodiments theFFE is fractionally spaced and produces “n” output samples for everydecision device output. The FFE output is decimated n:1 to maintainproper sample data alignment. Alternatively, in other embodiments theequalizer down-samples the data at the input of the decision device.This allows other elements of system 20 to take advantage of theincreased bandwidth associated with the fractionally spaced samples.

In certain other embodiments, the FFE output rate is not related to thedecision device symbol rate by a simple integer multiple relationship.As a non-limiting example, the FFE output may provide 4/3 the number ofsamples than the decision device symbol rate. In certain embodiments,selecting the sample nearest to the decision device symbol sample timedecimates the FFE output. In other embodiments, a sample rate converteris used to down-sample the FFE output. As non-limiting examples, thesample rate conversion process may occur at the FFE output, adder inputor adder output. Thus, although not shown in FIG. 5, it will beunderstood that some embodiments of equalizer 200 include a fractionallyspaced FFE wherein the samples in FFE 210 and DFE 216 are temporallyrelated but not necessarily temporally aligned to the same samplespacing.

Still other embodiments of the equalizer, having temporally relatedsamples in the FFE 210 and DFE 216, transfer the coefficient values fromthe FFE 210 to the DFE 216 to improve initial DFE startup andconvergence. As an example, some systems first enable the FFE 210 andadapt the FFE coefficients to reduce the channel distortion. After theFFE coefficients are relatively stable or the bit error rate is reducedto a desired threshold level, the system enables the DFE 216 and thecoefficients of the FFE 210 and DFE 216 are thereafter jointly adapted.The system then determines what temporally related sample the FFE 210and DFE 216 should use based on the delay of the channel. The samples tobe used by the FFE 210 and DFE 216 are adjusted as the delay of thechannel moves.

Some embodiments of the present invention adaptively change thetechnique used to evolve the equalizer tap coefficients to removechannel interference and ghosts. Illustratively, certain embodimentsadapt the equalizer tap coefficients in FFE 210 and DFE 216 to minimizethe least mean square (LMS) error between the equalizer output anddecision device output. This technique evolves the equalizer tapcoefficients over time in response to changing channel or systemconditions. Illustratively, some adaptation algorithms initially use anRCA technique to drive the LMS adaptation algorithm, then switch to adecision directed technique or combination of different adaptationstrategies dependent upon the channel conditions prior to applying adecision directed equalizer coefficient adaptation process.

Some embodiments of equalizer 200 improve the stability of the equalizerby limiting the magnitudes of certain DFE coefficients. With continuingreference to FIG. 19C, control system 54 (FIG. 5) limits the magnitudesof the DFE coefficients as a function of the tap index of the tap withwhich the coefficient is associated. In some embodiments, the range ofvalues of the DFE coefficients is divided into regions. Those taps withsmaller tap indices (i.e., most proximate to Z_(OUT)) have a firstpre-set range of magnitude limits. A second group of DFE taps have asecond pre-set range of allowable magnitudes. Finally, those DFE tapswith the largest tap indices (i.e., those furthermost from Z_(OUT)) havea third pre-set range of magnitude limits. As a first non-limitingexample, assuming the coefficients have a maximum magnitude of 1, thosetaps most proximate to Z_(OUT) have a maximum coefficient magnitude of0.85. The second group of DFE taps, located farther from Z_(OUT), has amaximum coefficient magnitude of 0.95. Finally, those DFE tapsfurthermost from Z_(OUT) have a maximum coefficient magnitude of 1.

In some embodiments, the maximum coefficient magnitude of those tapsmost proximate to Z_(OUT) can have a range between 0.75 and 0.85. Inother embodiments, the maximum coefficient magnitude of the second groupof taps, located between the furthermost taps and those proximate toZ_(OUT), have a range between 0.925 and 0.95. In still otherembodiments, those DFE taps furthermost from Z_(OUT) have a maximumcoefficient magnitude ranging from 0.95 to 1.

It will be appreciated that the DFE taps can be broken into fewer ormore groups and that the relative maximum coefficient magnitudes aredependent upon the number of DFE taps and their tap indices (locationrelative to Z_(OUT)). Illustratively, in some embodiments, only aportion of the DFE taps is limited. It will also be appreciated that inthose embodiments, limiting the magnitudes of the DFE coefficients withsmaller tap indices reduces the impact of decision errors made by thetrellis decoder.

Other embodiments of equalizer 200 apply a drain function to thecoefficients of the FFE and DFE. In some embodiments, the drain functionis a constant drain and reduces the magnitude of the coefficient by acontrolled amount on a regular basis. In other embodiments, the drainfunction is non-linear and tends to eliminate smaller coefficient valuesmore rapidly than larger coefficient values. In still other embodiments,the drain function is proportional and reduces the coefficientmagnitudes fractionally on a regular basis.

Some embodiments of the equalizer 200 apply a drain function, whereinthe controlled amount is varied in accordance with the tap index sothat, for example, magnitudes of coefficients of DFE taps with highertap indices are reduced at faster rate (or, alternatively, by a greateramount) than magnitudes of coefficients of taps with smaller tapindices. The variation of the controlled amount may be a function of thetap index or the taps may be grouped by ranges of tap indices and aseparate controlled amount may be applied to each group. In some otherembodiments of the equalizer 200, the controlled amount may be varied inaccordance with the operational stage of the equalizer, so that, forexample, the magnitudes of coefficients may be reduced by a smallercontrolled amount when the equalizer is starting up and then reduced bya larger controlled amount when the equalizer is operating in a steadystate mode. Similarly, the controlled amount may be varied in accordancewith the performance of the equalizer. In this case, for example, asmaller controlled amount may be used to reduce the magnitudes of thecoefficients when the SNR is relatively low and a larger controlledamount may be used as the SNR improves. In still further embodiments,taps farther from the virtual center of the FFE are drained at a fasterrate than FFE taps closer to the virtual center.

As a non-limiting example, and with reference to FIGS. 5, 6, and 21,some embodiments of system 20 include a technique, embodied by a system740 the operation of which is shown in FIG. 21, for developing anoverlapped equalizer structure or an equalizer without a reference orcenter tap. At 742, “Initialization,” control system 54 initializes thevarious portions of system 20 as will be understood by those skilled inthe art. Control system 54 then transitions system 740 to 744.

At 744, “CDE Estimate,” system 20 estimates the delay associated withthe transmission channel and determines the values of SEGMENT_SYNC_OUTand FRAME_SYNC_OUT. System 20 fixes the delay offset of the trainingsequence relative to its own system clock, symbol counter 316, andsequence counter 318. As a non-limiting example, in some embodimentssystem 20 uses a segment sync technique for determining the CDE. Inother embodiments system 20 uses a frame sync technique for determiningthe CDE. In still other embodiments system 20 uses a combination ofsegment sync and frame sync techniques to determine the CDE. Controlsystem 54 then transitions system 740 to 746.

At 746, “FFE Enable,” control system 54 enables the FFE portion of theequalizer of system 20. The DFE portion of the equalizer of system 20 isdisabled. Control system 54 develops the FFE coefficients dynamicallyusing an adaptation error signal generated based on the desired orexpected arrival of the synchronization signal embedded within thetransmission. Illustratively, in some embodiments of system 20, whichinclude equalizer 200A, control system 54 generates (or causes to begenerated) synchronization signals at the desired or expected temporallocation based on the CDEU 230 estimate of the CDE. Illustratively,control system 54 generates a segment sync training signal for adaptingequalizer 20 when SC=SEGMENT_SYNC_OUT.

Control system 54 then creates an adaptation error signal by subtractingequalized data signal 88 from the generated synchronization signalsgenerated by control system 54. Control system 54 chooses the portion ofthe adaptation error based upon a windowing technique to adapt thecoefficients of the equalizer. The window chosen depends upon theoperational state of system 20. For example, in some embodiments controlsystem 54 uses the segment sync signal to adapt the FFE coefficientsduring initial system startup. In other embodiments, control system 54uses the field/frame sync signal to adapt the FFE coefficients duringinitial system startup. In still other embodiments, control system 54first uses the segment sync signal to adapt the FFE coefficients, andthereafter transitions to use the field/frame sync signal in combinationwith the segment sync signal.

As discussed later, once reliable synchronization is obtained, controlsystem 54 adapts the FFE coefficients based upon the desired or expectedtemporal locations of the synchronization signals as determined by theCDEU estimate of the CDE. Control system 54 generates synchronizationsignals at the desired or expected temporal location based upon the CDEUestimate of the CDE. Control system 54 then creates an adaptation errorsignal by subtracting the received signal from a generatedsynchronization signal. Control system 54 then uses the adaptation errorsignal to adapt the coefficients of the FFE based upon an adaptationerror signal.

Illustratively, in some embodiments, control system 54 generates anadaptation difference signal by subtracting the received signal from areceiver generated segment sync signal. Some embodiments generate anadaptation difference signal by subtracting the received signal from areceiver generated frame sync signal. Still other embodiments firstadapt the FFE coefficients based upon the expected arrival of thesegment sync signal. After a particular level of performance is reached,such as detecting the presence of a reliable frame sync signal, controlsystem 54 generates the difference signal generated using both a segmentsync signal and field/frame sync signal.

In some embodiments, control system 54 transitions system 740 operationto 742 if reliable synchronization signals are not detected after someperiod of time. Similarly, in some embodiments, control system 54transitions system 740 to 742 if it detects a loss of the field/framesync signal. Otherwise, control system 54 transitions system 740 to 748when the equalizer output SNR performance (based upon the SNR of thereceived synchronization signals) is greater than a predeterminedDFE_ENB Threshold. Hysteresis may be provided by selecting DFE_ENBThreshold>RETURN_FFE Threshold.

At 748, “DFE Enabled,” control system 54 enables the DFE portion 216 ofthe equalizer 200 that acts as an infinite impulse response (IIR)filter. Control system 54 uses the adaptation error signal generatedbased on the segment sync signal and the field/frame sync signal toadapt the equalizer's FFE and DFE coefficients. The adaptation errorsignal generation is similar to that used in “FFE Enabled” 746. The datainput into the DFE is quantized to a level depending upon the precisionavailable through the DFE delay path.

Control system 54 transitions system 740 to 742 if it detects the lossof the field/frame sync signal. Otherwise, control system 54 transitionssystem 740 to 750 when the equalizer output SNR performance is greaterthan a predetermined RCA_ENB Threshold, where the signal to noiseperformance is based upon the SNR of the received synchronizationsignals. However, in some embodiments, control system 54 transitionssystem 740 to 746 when the equalizer output SNR performance falls belowa RETURN_FFE Threshold. Hysteresis may be incorporated by selectingRCA_ENB Threshold>RETURN_DFE Threshold>DFE_ENB Threshold. Someembodiments use other techniques known in the art such as averagingfilters and continuity counters to improve the performance of thesystem.

At 750, “RCA,” the FFE and the DFE coefficients are updated using theadaptation error signal based on a reduced constellation algorithm(RCA). The RCA assumes the input data are 2-leveled, so the referencesignal generated locally is a binary slice of the incoming data.Illustratively, in some embodiments of system 20 that include equalizer200A, control system 54 generates the adaptation error signal bysubtracting equalized data signal 88 from adaptation symbol decision 94of decision device 214. Control System 54 configures adaptation symboldecision 94 to provide the binary slice of the incoming data from theequalized data signal 88. The binary slicer maps an 8-VSB signal withnormalized levels at −7, −5, −3, −1, +1, +3, +5, +7 to −5.25 and +5.25.In some embodiments, slicing is done on a two level basis. In otherembodiments slicing is accomplished on a four level basis. Still otherembodiments like CMA use the kurtosis of the signal constellation.Finally, other embodiments use other reduced constellation techniquesknown to those skilled in the art. The adaptation error signal is usedto update both the FFE and the DFE coefficients. As before, the datainto the DFE is quantized sliced data (8- or 16-level decision slicer)and the DFE acts as an IIR filter.

In some embodiments, control system 54 adapts the FFE and DFEcoefficients using only an RCA algorithm on the received data. In otherembodiments, control system 54 compares the received synchronizationsignals to those generated by control system 54. In still otherembodiments, control system 54 weights the effects of the RCA andsynchronization signal-based adaptation techniques depending upon systemperformance or operational state.

If control system 54 detects the loss of the field/frame sync signal,control system 54 transitions system 740 to 742. Otherwise, controlsystem 54 transitions system 740 to 752 when the equalizer output SNRperformance becomes greater than DATA_DIRECTED Threshold. In someembodiments, the technique for calculating SNR includes examining bothreceived synchronization signals and data signals. If, instead ofimproving, the system SNR performance falls below the RETURN_DFEThreshold, then control system 54 transitions system 740 to 748.Hysteresis may be incorporated by selecting DATA_DIRECTEDThreshold>RCA_ENB Threshold>RETURN_RCA Threshold.

At 752, “Trellis Decoder Enabled,” the FFE and DFE taps are updatedusing an adapted error signal generated based on the trellis decoderoutput. Similar to before, control system 54 configures adaptationsymbol decision 94 to provide an output from the trellis decoder.Control system 54 uses a decision directed LMS technique for adaptingthe equalizer coefficients. In some embodiments, the adaptive errorsignal is determined by looking at the output of trellis decoding of the8-VSB signal. In other embodiments, the adaptive error signal isdetermined by examining the output of one of the trellis decoder stages.Similar to before, the data input into the DFE is quantized sliced datato a predetermined number of levels, and the DFE acts as an IIR filter.

As above, control system 54 transitions system 740 to 742 if it detectsthe loss of the field/frame sync signal. Otherwise, control system 54transitions system 740 to 754 when the equalizer output SNR performancebecomes greater than DFE_UPDATE Threshold. If, instead of improving theSNR performance of the system falls below the RETURN_RCA Threshold, thencontrol system 54 transitions system 740 to 752. Hysteresis may beincorporated by selecting DFE_UPDATE Threshold>RETURN_RCAThreshold>RCA_ENB Threshold.

At 754, “DFE Decision Update,” system controller 54 updates the FFE andDFE coefficients using the adaptation error signal generated based onthe trellis decoded output. In addition, controller 54 configures thedecision device of the equalizer to provide trellis-decoded data intothe DFE 216. Illustratively, in some embodiments of system 20, whichinclude equalizer 200A, control system 54 selectively controls equalizerfeedback signal 92 to provide trellis decoder corrected data to DFE 216.In other embodiments, control system 54 selectively controls equalizerfeedback signal 92 to update DFE 216 with corrected data from thevarious stages of the trellis decoder. Thus, DFE 216 initially receivesthe decision slicer output of decision device 214. The trellis decoderportion of decision device 214 then updates the DFE received decisionsas corrections become available. Still another embodiment operates byproviding trellis decoder updated values from intermediate stages of thetrellis decoder to stages of the DFE as described in co-pending U.S.patent application Ser. Nos. 10/407,610, entitled “Transposed Structurefor a Decision Feedback Equalizer Combined with a Trellis Decoder,” and09/884,256, entitled “Combined Trellis Decoder and Decision FeedbackEqualizer.”

As above, control system 54 transitions system 740 to 742 if it detectsthe loss of the field/frame sync signal. Otherwise, control system 54transitions 740 to 752 if the equalizer output SNR performance fallsbelow the RETURN_TRELLIS_ENABLE Threshold.

Some embodiments of system 20 use an average magnitude of the adaptationerror signal in place of SNR. Other embodiments of system 20 use the biterror rate detected by a trellis decoder. Still other embodiments ofsystem 20 use the bit error rate of FEC symbol decision 80. Still otherembodiments, similar to U.S. Pat. No. 6,829,297 also modify theadaptation process depending upon performance metrics developed by thetrellis decoder. It will be understood that system 740 may be adaptedfor systems without trellis decoding by omitting certain steps.Likewise, the transition point may be adjusted for optimum performancedepending upon the operating conditions and application. In addition tohysteresis provided by the transition threshold levels, some embodimentsof system 20 also include a confidence counter, averaging filter, orsimilar transition smoothing technique to improve stability andcounteract momentary shifts in system performance.

It will be understood that in some embodiments system 740 can besimplified by eliminating intermediate stages between 746 and 754.Illustratively, embodiments not having a trellis decoder or notincluding as a feature the ability of the trellis decoder to update thesample within the DFE do not need stages 752 or 754.

Another embodiment of equalizer 46, illustrated as equalizer 200A inFIG. 22, is similar in form and function to equalizer 200 except for theaddition of a phase tracker 240 between the output of FFE 210 and thefirst input of adder 212. As shown in FIG. 22, phase tracker 240receives an input from FFE 210 and feedback signals 246, and provides anoutput to adder 212. As described later in detail, phase tracker 240receives a variety of feedback signals 246. The feedback signals 246 mayinclude one or more signals of interest generated by or within system20. Illustratively, in some embodiments of system 20 the feedbacksignals 246 include equalized data signal 88. In yet other embodiments,feedback signals 246 include equalized data signal 88 andsynchronization symbol decision 86. In still other embodiments, feedbacksignals 246 include intermediate equalizer signal 90, equalized datasignal 88 and equalizer feedback signal 92. As described later, phasetracker 240 uses the feedback signals to develop a phase correctionvector that is used to correct the output of FFE 210.

One embodiment of phase tracker 240 in equalizer 200A is phase tracker800A as illustrated in FIG. 23, which receives input signal 242 from FFE210 and feedback signals 246A and 246B. Feedback signal 246A is the sineof the estimated phase error (i.e., sin θ) present in the receivedsignal. Similarly, feedback signal 246B is the cosine of the estimatedphase error (i.e. cos θ) present in the received signal. The output ofphase tracker 800A is an input of adder 212 of equalizer 200A.

Phase tracker 800A includes delay line 810, phase-shift filter 812,rotator 814, integrator 816, subtractor 818 and multipliers 822, 824 and826. Phase tracker 800A produces phase tracker decision error signal(E_(PTD)) 248 by taking the difference between an output of the decisiondevice 214 and the corresponding equalized data signal 88. Asillustrated in FIG. 23, at least one embodiment includes subtractor 830and delay element 832. The input of delay element 832 receives equalizeddata signal 88, which is the output of adder 212. The negating andpositive inputs of subtractor 830 respectively receive the delayedequalized data signal 88 from delay element 832 and an output ofdecision device 214. The output of subtractor 830 is phase trackerdecision error signal (E_(PTD)) 248. Thus, the phase tracker decisionerror signal (E_(PTD)) 248 is developed by taking the difference betweenthe output of decision device 214 and the appropriately delayedequalized data signal 88. As such, the phase tracker decision errorsignal (E_(PTD)) 248 is the error between the decision output and theinput that generated that output. Delay element 832 provides sufficientsignal propagation delay to allow for the correct temporal alignment ofinputs into subtractor 830 and varies depending on the nature of theoutput of decision device 214.

Illustratively, some embodiments develop phase tracker decision errorsignal (E_(PTD)) 248 by subtracting an appropriately delayed equalizeddata signal 88 from the decision slicer output of decision device 214.Still other embodiments develop the phase tracker decision error signal(E_(PTD)) 248 by subtracting an appropriately delayed equalized datasignal 88 from a trellis decoder output of decision device 214. Yetother embodiments develop the phase tracker decision error signal(E_(PTD)) 248 by subtracting an appropriately delayed equalized datasignal 88 from an intermediate output stage in a trellis decoder ofdecision device 214. Certain embodiments develop phase tracker decisionerror signal (E_(PTD)) 248 by subtracting appropriately equalized datasignal 88 from the adaptation symbol decision 94 of decision device 214.In still other certain embodiments, control system 52 selects the outputof decision device 214 used to create phase tracker decision errorsignal 248 depending upon the state of the system, the equalizer and/orchannel conditions.

Phase tracker 800A develops a phase error feedback signal as will beunderstood by those skilled in the art. Delay line 810 and phase-shiftfilter 812 receive input signal 242, which is the output of FFE 210.Delay line 810 provides an output to the in-phase signal input ofrotator 814 and multiplier 826. Multiplier 826 also receives feedbacksignal 246A, sin θ. Phase-shift filter 812 provides an output to boththe quadrature signal input of rotator 814 and multiplier 824.Multiplier 824 also receives feedback signal 246B, cos θ.

In some embodiments, phase-shift filter 812 includes a 90-degreephase-shift filter or quadrature filter. In other embodiments,phase-shift filter 812 includes a Hilbert filter or truncated Hilbertfilter. In still other embodiments, phase-shift filter 812 is a FIRfilter of some desired length with filter tap coefficients optimized tominimize the mean square error (MMSE) of the filter output for a channelthat is 90-degrees phase-shifted and a particular receiver acquisitionthreshold. Illustratively, some embodiments of phase-shift filter 812are a FIR filter that has a length of 31 samples and MMSE-optimizedfilter tap coefficients for a VSB or offset-QAM receiver acquisition SNRthreshold of 15.1 dB. Other embodiments of phase-shift filter 812include filter tap values optimized for a receiver acquisition SNRthreshold of less than 15.1 dB. At least one embodiment of the presentinvention includes phase-shift filter 812 coefficients optimized for anacquisition SNR threshold of 15 dB.

The negating and positive inputs of subtractor 818 receive the outputsof multiplier 826 and multiplier 824 respectively. Subtractor 818provides a phase error estimate to multiplier 822, which also receivesphase tracker decision error signal (E_(PTD)) 248 from subtractor 830.Integrator 816 receives the output of multiplier 822 and provides aphase correction signal θ to the input of rotator 814. Finally, rotator814 provides a phase-corrected output to adder 212 of equalizer 200A.

In some embodiments, phase tracker 800A receives the output of FFE 210as a real or in-phase signal I_(FFE). The output of FFE 210 is passedthrough phase-shift filter 812 to create a corresponding imaginary orquadrature signal Q_(FFE).

The output of FFE 210 is also passed through delay line 810 to insurethat I_(FFE) and Q_(FFE) are temporally aligned and correspond to thesame FFE 210 output. I_(FFE) and Q_(FFE) can be thought of as a vectorpair that has a magnitude and phase. However, it will be understood thatsome embodiments of FFE 210 receiving I_(F) and Q_(F) will output both areal and phase-quadrature component without need of delay line 810 andphase-shift filter 812. Phase tracker 800A minimizes the phase errorpresent at the output of equalizer 200A by rotating I_(FFE) and Q_(FFE).Rotator 814 multiples I_(FFE) and Q_(FFE) by a phase correction vector,e^(jθ), based upon the phase correction signal θ provided by integrator816 where the input to integrator 816 is E_(PTD)·(Q_(FFE) cos θ−I_(FFE)sin θ) and E_(PTD) is the phase tracker decision error signal temporallyrelated to the feedback signals 246A and 246B. Thus, the input to theintegrator is a decision directed phase error signal related to aparticular output of FFE 210. As such, the output of integrator 816 isphase correction signal θ, where at sample index i,θ_(i)=θ_(i-1)+μ·E_(PTD)·(Q_(FFE) cos θ_(i-1)−I_(FFE) sin θ_(i-1)) whereμ is some update step size parameter. It can be appreciated that in someembodiments the range of values for θ is limited.

Rotator 814 rotates the vector pair I_(FFE) and Q_(FFE) using the phasecorrection signal θ. In some embodiments rotator 814 includes a complexmultiplier, sine look-up table and cosine look-up table. Rotator 814translates the received phase correction signal θ into thephase-correction vector e^(jθ), which is used to rotate I_(FFE) andQ_(FFE). Rotator 814 produces a phase-corrected in-phase or real signalI_(PT). In some embodiments rotator 814 also produces a quadrature orimaginary signal Q_(PT) (not shown). As will be understood by thoseskilled in the art, these illustrations are by way of example and otherdelay elements, not shown in FIG. 23, will be included in someembodiments to maintain the correct temporal relationships between thevarious signals.

The phase error feedback signal is created by estimating the phase errorpresent in a stage of equalizer 200A (see FIG. 22). Some embodiments ofphase tracker 800A estimate the phase error present in one of theequalizer output signals depending upon the operational mode of theequalizer. Illustratively, in some embodiments the phase error estimateis derived from the output of FFE 210. In other embodiments the phaseerror estimate is derived from the output of adder 212 of equalizer200A. In still other embodiments the phase error estimate is derivedfrom an output of phase tracker 800A. In yet other embodiments, thesignal used to derive the phase error estimate is selected by controlsystem 54 depending upon equalizer performance.

Another embodiment of phase tracker 240 is shown in FIG. 24 as 800B.Phase tracker 800B is operationally similar to phase tracker 800A exceptthat signals I_(FFE) and Q_(FFE) are first multiplied by the phasetracker decision error signal 248. As such, phase tracker 800B includesmultiplier 822 in a different position, and further includes anadditional multiplier 828.

Multiplier 826 receives as inputs I_(FFE) and phase tracker error signal(E_(PTD)) 248. Multiplier 822 receives as inputs feedback signal 246A(sin θ) and the output of multiplier 826. Multiplier 828 receives asinputs Q_(FFE) and phase tracker error signal (E_(PTD)) 248. Multiplier824 receives as inputs feedback signal 246B (cos θ) and the output ofmultiplier 828. The negating and positive inputs of subtractor 818receive the outputs of multipliers 822 and 824 respectively, and thedifference is provided as an output to integrator 816. As in phasetracker 800A, integrator 816 receives the output of subtractor 818, andprovides phase correction signal θ to the input of rotator 814. Finally,rotator 814 provides a phase-corrected output to adder 212 of equalizer200A.

The phase correction signal θ of phase tracker 800B for sample index iis θ_(i)=θ_(i-1)+μE_(PTD)·(Q_(FFE) cos θ_(i-1)−I_(FFE) sin θ_(i-1))where the feedback signal 246A, sin θ, and feedback signal 246B, cos θ,are related to the phase tracker decision error signal E_(PTD). Asbefore, rotator 814 multiplies the incoming data vectors I_(FFE) andQ_(FFE) by the phase correction vector e^(jθ) and thereby corrects thephase of the output of FFE 210. As will be understood by those skilledin the art, these illustrations are by way of example only and otherdelay elements, not shown in FIG. 24, are used in various embodiments tomaintain the correct temporal relationships between the various signals.

Another embodiment of phase tracker 240, in equalizer 200A, is phasetracker 800C adapted for VSB and offset QAM modulation systems. Asillustrated in FIG. 25, phase tracker 800C receives input signal 242from FFE 210, and phase tracker decision error signal (E_(PTD)) 248. Theoutput of phase tracker 800C connects to the input of adder 212 ofequalizer 200A. As shown in FIG. 25 phase tracker 800C employs similartechniques as used in phase tracker 800A to generate the phase trackerdecision error signal (E_(PTD)) 248.

Similar to phase tracker 800A, phase tracker 800C also includes delayline 810, phase-shift filter 812, rotator 814, integrator 816 andmultiplier 822. The inputs of delay line 810 and phase-shift filter 812receive input signal 242 from FFE 210 and have as outputs I_(FFE) andQ_(FFE) respectively. The output of delay line 810 provides I_(FFE),which is a delayed version of input signal 242, to the in-phase signalinput of rotator 814. The output of phase-shift filter 812 providesQ_(FFE) to the quadrature signal input of rotator 814 and multiplier828. As a result, Q_(FFE) is used as a phase error signal. Multiplier822 also receives the phase tracker decision error signal (E_(PTD)) 248and provides the product as an input to integrator 816. Integrator 816provides phase correction signal θ to the input of rotator 814.

Similar to the previously described phase trackers, passing the outputof FFE 210 through delay line 810 and phase-shift filter 812 creates thesignals I_(FFE) and Q_(FFE). Multiplier 822 multiplies Q_(FFE) by thephase tracker decision error signal 248 to produce a decision directedphase error estimate, which is then integrated by integrator 816 to formphase correction signal at sample index i,θ_(i)=θ_(i-1)+μ·(Q_(FFE))·(E_(PTD)). Rotator 814 receives θ and developsphase correction vector e^(jθ). Rotator 814 multiplies the vector pairI_(FFE) and Q_(FFE) by the phase correction vector e^(jθ) to produce thephase-corrected real or in-phase output. As will be understood by thoseskilled in the art, these illustrations are by way of example. Otherdelay elements (not shown in FIG. 25), are used in some alternativeembodiments to maintain the correct temporal relationships between thevarious signals depending upon the latency in developing the phasetracker decision error signal. Illustratively, it will be understoodthat the phase error estimate and phase tracker decision error signal248 correspond to the output of FFE 210. However, since the output ofmultiplier 822 is integrated to obtain an average phase correctionsignal, in some embodiments the phase correction signal e^(jθ) appliedto I_(FFE)(n) and Q_(FFE)(n) may not include a contribution fromI_(FFE)(n) and Q_(FFE)(n); it will be understood that I_(FFE)(n) andQ_(FFE)(n) are the n^(th) I_(FFE) and Q_(FFE) samples.

Another embodiment of phase tracker 240 in equalizer 200A is phasetracker 800D, which is also adapted for VSB and offset QAM modulationsystems. As illustrated in FIG. 26, phase tracker 800D receives inputsignal 242 from FFE 210, and phase tracker decision error signal(E_(PTD)) 248 and provides an output to adder 212 of equalizer 200A. Asshown in FIG. 26, phase tracker 800D uses similar techniques aspreviously described in relation to phase tracker 800A to generate thephase tracker decision error signal (E_(PTD)) 248. Phase trackerdecision error signal (E_(PTD)) 248, shown as part of phase tracker800D, is similar in form and function to that used in phase tracker800A.

Similar to phase tracker 800C, phase tracker 800D also includes delayline 810, phase-shift filter 812, rotator 814, integrator 816 andmultiplier 822. As with the previously described phase trackers, theinputs of delay line 810 and phase-shift filter 812 receive input signal242 from FFE 210, and produce I_(FFE) and Q_(FFE) at their respectiveoutputs. Rotator 814 receives I_(FFE) and Q_(FFE) at its in-phase andquadrature inputs, respectively. Rotator 814 produces a phase-correctedin-phase or real signal I_(PT) and quadrature or imaginary signalQ_(PT). Adder 212 of equalizer 200A receives the real signal I_(PT) asan input. Multiplier 822 receives the quadrature Q_(PT) of rotator 814and phase tracker decision error signal (E_(PTD)) 248. Multiplier 822provides the product of Q_(PT) and E_(PDT) to integrator 816. Integrator816 integrates the output of multiplier 822 to produce phase correctionsignal θ as an output to the correction vector input of rotator 814.

Phase tracker 800D uses the product of E_(PTD) and Q_(PT) as the phaseerror estimate at the output of rotator 814. Multiplier 822 multipliesQ_(PT) by the phase tracker decision error signal 248 to produce adecision directed phase error estimate, which is then integrated byintegrator 816 to form phase correction signalθ_(i)=θ_(i-1)+μ·(Q_(PT))·(E_(PTD)). Rotator 814 receives θ and developsphase correction vector e^(jθ). In some embodiments the maximum phasecorrection is limited to a desired range. As a non-limiting example, insome embodiments the maximum phase correction signal limits the phasecorrection provided by rotator 814 to ±45 degrees. Rotator 814 thenmultiplies the vector pair I_(FFE) and Q_(FFE) by the phase correctionvector e^(jθ) to produce the phase-corrected real or in-phase outputI_(PT). As will be understood by those skilled in the art, theseillustrations are by way of example. Other delay elements, not shown inFIG. 26, are used in some embodiments to maintain the temporalrelationship between phase error estimate Q_(PT) and phase trackerdecision error signal E_(PTD) such that the output of multiplier 822 isthe decision directed phase error estimate corresponding to an outputfrom FFE 210 (input signal 242).

Still another embodiment of phase tracker 240 in equalizer 200A is phasetracker 800E, which is also adapted for VSB and offset QAM modulationsystems. As illustrated in FIG. 27, phase tracker 800E receives inputsignal 242 from FFE 210 and provides the phase-corrected real orin-phase output I_(PT) to adder 212 of equalizer 200A. Similar to theembodiments discussed above, as shown in FIG. 27, phase tracker 800Euses similar techniques and devices as previously described in relationto phase tracker 800A to generate the phase tracker decision errorsignal (E_(PTD)) 248. Phase tracker decision error signal (E_(PTD)) 248,shown as part of phase tracker 800E, is similar in form and function tothat used in phase tracker 800A.

As with phase tracker 800D, phase tracker 800E also includes delay line810, phase-shift filter 812, rotator 814, integrator 816 and multiplier822. The inputs of delay line 810 and phase-shift filter 812 receiveinput signal 242 from FFE 210. Delay line 810 and phase-shift filter 812then provide I_(FFE) and Q_(FFE), respectively, to the in-phase andquadrature inputs of rotator 814. Rotator 814 receives phase correctionsignal θ from integrator 816 and provides phase-corrected in-phase orreal signal I_(PT) to adder 212 of equalizer 200A.

Phase tracker 800E further includes phase-shift filter 840 that hassimilar function and properties to phase-shift filter 812. In certainembodiments as shown in FIG. 27, phase-shift filter 840 receivesequalized data signal 88. In certain other embodiments, not shown, theinput of phase-shift filter 840 receives an output from decision device214. Illustratively, in some embodiments, phase-shift filter 840receives the output of a decision slicer within decision device 214. Inother embodiments, phase-shift filter 840 receives the output of atrellis decoder in decision device 214. In still other embodiments,phase-shift filter 840 receives an output from one of the stages of atrellis decoder in decision device 214. Alternatively, in someembodiments of 800E (not shown), phase shift filter 840 receives I_(PT)instead of equalized data signal 88.

The inputs of multiplier 822 receive the outputs of phase-shift filter840 and phase tracker decision error signal (E_(PTD)) 248. As shown inFIG. 27, phase-shift filter 840 receives the equalized data signal 88and provides an imaginary or quadrature signal Q_(EQ) as an output tomultiplier 822. Q_(EQ) is the phase error estimate for the equalizeroutput provided to phase-shift filter 840. Multiplier 822 produces adecision directed phase error estimate by multiplying Q_(EQ) by thephase tracker decision error signal (E_(PTD)) 248. Integrator 816integrates the output of multiplier 822 to form phase correction signalθ_(i)=θ_(i-1)+μ·(Q_(EQ))·(E_(PTD)). Rotator 814 receives phasecorrection signal θ and develops phase correction vector e^(jθ). Rotator814 then multiplies the vector pair I_(FFE) and Q_(FFE) by the phasecorrection vector e^(jθ) to produce the phase-corrected real or in-phaseoutput I_(FFE). As will be understood by those skilled in the art, theseillustrations are by way of example. Other delay elements not shown inFIG. 27 are used in some embodiments to maintain the temporalrelationship between phase error estimate Q_(EQ) and E_(PTD) such thatthe output of multiplier 822 is the decision directed phase errorestimate corresponding to a particular recovered symbol.

An additional embodiment of phase tracker 240 in equalizer 200A is phasetracker 800F, as illustrated in FIG. 28, which includes first delay line810, phase-shift filter 812, rotator 814 and integrator 816. Phasetracker 800F receives input signal 242 from FFE 210 at delay line 810and phase-shift filter 812. Delay line 810 and phase-shift filter 812provide I_(FFE) and Q_(FFE), respectively, to the in-phase andquadrature inputs of rotator 814.

Phase tracker 800F further includes subtractor 818, multiplier 822,multiplier 824, delay line 836, delay line 838, phase-shift filter 840and delay line 842. Delay lines 836 and 838 receive I_(FFE) and Q_(FFE),respectively. Delay line 836 provides a delayed version of I_(FFE) toone input of multiplier 822. Delay line 838 provides a delayed versionof Q_(FFE) to one input of multiplier 824. As shown in FIG. 28, in someembodiments delay line 842 and phase-shift filter 840 receives an outputfrom decision device 214. Illustratively, in some embodiments, adecision slicer of decision device 214 provides the output to delay line842 and phase-shift filter 840. In other embodiments, a trellis decoderof decision device 214 provides the output to delay line 842 andphase-shift filter 840. In still other embodiments, one of the stages ofa trellis decoder of decision device 214 provides the output to delayline 842 and phase-shift filter 840. Yet other embodiments alternativelyprovide the equalized data signal 88 at the input of decision device 214as an input to delay line 842 and phase-shift filter 840. In addition,certain other embodiments of phase tracker 800F select the input tophase-shift filter 840 and delay line 842 depending upon the operationalstate of the equalizer 200A or system 20.

Phase-shift filter 840 produces quadrature output Q_(DD). Delay line 842provides a delayed version of the in-phase input as output I_(DD). Aswill be appreciated that delay line 842 compensates for the delayintroduced by phase-shift filter 840 and temporally aligns Q_(DD) andI_(DD).

It will also be appreciated that delay lines 836 and 838 compensate fordelay introduced by signal processing in equalizer 200A and temporallyalign the delayed versions of I_(FFE) and Q_(FFE) with I_(DD) andQ_(DD). Thus, multiplier 822 receives Q_(DD) and a delayed version ofI_(FFE) from phase-shift filter 840 and delay line 836, respectively.Similarly, multiplier 824 receives I_(DD) and a delayed version ofQ_(FFE) from delay lines 842 and 838, respectively. The delay providedby delay lines 836 and 838 aligns the inputs to multiplier 822 and 824such that they correspond to the same received symbol.

The negating and positive inputs of subtractor 818 receive the outputsof multiplier 822 and multiplier 824, respectively, and subtractor 818provides a decision directed phase error output to integrator 816.Similar to previous phase tracker embodiments, integrator 816 provides aphase correction signal θ to rotator 814 whereθ_(i)=θ_(i-1)+μ·[(Q_(FFE)·I_(DD))−(I_(FFE)·Q_(DD))].

Rotator 814 receives θ and develops phase correction vector e^(jθ).Rotator 814 multiplies the vector pair I_(FFE) and Q_(FFE) by the phasecorrection vector e^(jθ) to produce the phase-corrected real or in-phaseoutput I_(PT). As will be understood by those skilled in the art, theseillustrations are by way of example. Other delay elements, not shown inFIG. 28, are used in some embodiments to maintain the temporalrelationship between I_(F), Q_(FFE), I_(DD), and Q_(DD) at multipliers822 and 824 such that the output of subtractor 818 is the decisiondirected phase error estimate corresponding to a particular recoveredsymbol.

Although phase tracker 800 and specific embodiments 800A-800F show FFE210 receiving only I_(F), it will be understood that some embodiments ofphase tracker 800 are adapted to embodiments of FFE 210 receiving I_(F)and Q_(F) and providing I_(FFE) and Q_(FFE) as outputs directly from FFE210 to rotator 814. Likewise, in some embodiments, the maximum phasecorrection range is limited. As a non-limiting example, some embodimentslimit the maximum phase correction provided by rotator 814 to ±45degrees. In still other embodiments, the value of θ is limited tocontrol the range of the phase correction signal. In addition, althoughdescribed in relation to an ATSC system, it will be understood that thetechniques and devices contained in embodiments of phase trackers 800can be adapted to other modulation techniques and data constellations.

Similarly, it will be understood that some embodiments of phase tracker800 are adapted to operate with embodiments of FFE 210 that havefractionally spaced samples. Finally, it will be understood that someembodiments of phase tracker 800 are adapted to receive both real andquadrature input signals as inputs from FFE 210; and therefore FFE 210directly provides I_(FFE) and Q_(FFE) without the need for delay line810 and phase shifter 812.

Another embodiment of system 20 of FIG. 3 is system 900 shown in FIG.29. According to one aspect, system 900 employs a technique fordeveloping a carrier tracking feedback loop and timing synchronizationfeedback loop. System 900 includes synchronization 910, digitaldemodulator 920, equalizer 930, decision directed control (DDC) 940,non-coherent control (NCC) 950 and control system 954, which areanalogous in form and function to elements 40, 42, 46, 52, 50 and 54 ofsystem 20 (see FIG. 3), respectively. Similar to system 20, system 900develops the previously described signals segment sync 96, field/framesync 98, SNR 100, VCXO lock 102, and NCO lock 104. Like control system54 of system 20, control system 954 receives segment sync 96,field/frame sync 98, SNR 100, VCXO lock 102, and NCO lock 104. It willalso be understood that various embodiments of equalizer 930 includepreviously described embodiments of equalizers 48, 200, and 200A.Likewise, some embodiments of equalizer 930 include previously describedembodiments of phase tracker 800, 800A, 800B, 800C, 800D, 800E, and800F.

In addition, signals 64A, 66A, 72A and 74A are similar in form andfunction to signals 64, 66, 72 and 74 of FIG. 3. It will be understoodthat for the sake of simplicity, Nyquist filtering of the digitaldemodulator output is not illustrated in system 900; however, this is byway of convenience and is not intended as a limitation. Those skilled inthe art will appreciate that Nyquist filtering occurs in any of avariety of forms in various embodiments of the present system.

As shown in FIG. 29, system 900 receives near-baseband signal 60A from afront end receiver (receiver 30 in FIG. 3, for example) and providesdigitized near-baseband signal 62A to digital demodulator 920. Theoutput of digital demodulator 920 provides a baseband signal 920A asinput to equalizer 930. Equalizer 930 provides outputs 930A, 930B, 930C,and 930D to decision directed control 940. DDC 940 includes subtractor942, carrier offset post filter 944, timing offset post filter 946,multiplier 948 and multiplier 950. DDC 940 provides a decision directedsynchronization feedback signal 66A to synchronization 910 and furtherprovides decision directed carrier tracking feedback signal 74A todigital demodulator 920.

In some embodiments, equalizer 930 is an overlapped equalizer. In otherembodiments, equalizer 930 does not have a predefined or fixed centertap. Certain embodiments of equalizer 930 also include a phase tracker.Thus, as explained in greater detail later, in some embodiments theoutputs 930A and 930B are partially equalized signals. Illustratively,in some embodiments, equalizer outputs 930A and 930B are the output ofthe FFE portion of equalizer 930. In other embodiments, equalizeroutputs 930A and 930B are the outputs of a phase tracker portion of anequalizer. In still other embodiments, equalizer outputs 930A and 930Bare the input signals to the decision device of the equalizer. In yetother embodiments, equalizer outputs 930A and 930B are provided bydifferent sources. As a non-limiting example, in some embodimentsequalizer output 930A is also the input signal to the decision device ofthe equalizer while equalizer output 930B is the output of the phasetracker of the equalizer.

Another aspect of system 900 is development of a decision error signalsimilar to phase tracker decision error signal (E_(PTD)) 248. Thus, insome embodiments, equalizer outputs 930C and 930D are the input signalto the decision device of equalizer 930 and the decision device outputcorresponding to the input signal 930C, respectively. In certainembodiments, the equalizer output 930D is the output of a decisionslicer of a decision device. In other embodiments equalizer output 930Dis the output of a trellis decoder. In still other embodiments, theequalizer output 930D is the output of an intermediate stage of atrellis decoder.

Using one or more delay elements (not shown), system 900 appliestechniques available to those skilled in the art to temporally aligndata presented to subtractor 942. Thus, subtractor 942 produces errorfeedback signal 942A, which is the difference between the decisiondevice output of equalizer 930 and the corresponding input to thedecision device. Similarly, system 900 also temporally aligns the inputspresented to multipliers 948 and 950. Thus, the inputs to multiplier 948correspond to the same baseband signal 920A. Likewise, the inputs tomultiplier 950 correspond to the same baseband signal 920A. Finally,although FIG. 29 shows multipliers 948 and 950 receiving the same errorfeedback signal 942A, it will be understood that this is by way ofexample and not intended as a limitation. Thus, in some embodiments, theerror signal used for carrier tracking is calculated differently thanthe error signal used for synchronization. Illustratively, in someembodiments, the error feedback signal 942A for carrier tracking isformed with the slicer output of equalizer 930, whereas the errorfeedback signal 942A for synchronization is formed with the trellisdecoder output of equalizer 930.

Carrier offset post filter 944 and timing offset post filter 946 receiveequalizer outputs 930A and 930B, respectively. The negating and positiveinputs of subtractor 942 receive equalizer outputs 930C and 930D,respectively, and produce error feedback signal 942A. Multiplier 948receives the outputs of carrier offset post filter 944 and errorfeedback signal 942A. Multiplier 948 provides decision directed carriertracking feedback signal 74A to loop filter 926. Similarly, multiplier950 receives the outputs of timing offset post filter 946 and errorfeedback signal 942A. Multiplier 950 provides a decision directedsynchronization feedback signal 66A to loop filter 916.

Carrier offset post filter 944 detects the carrier frequency and phaseoffset present in equalizer output 930A. In some embodiments, carrieroffset post filter 944 is a phase error detector that provides a phaseerror estimate. In other embodiments, carrier offset post filter 944 isa phase-shift filter or quadrature filter similar in form and functionto phase-shift filter 812. Thus, some embodiments of carrier offset postfilter 944 include a Hilbert filter or truncated Hilbert filter. Instill other embodiments, carrier offset post filter 944 is a FFE ofdesired length with filter tap coefficients optimized to minimize themean square error (MMSE) of the filter output for a channel that is90-degrees phase-shifted, and a receiver having a pre-determinedacquisition threshold.

Illustratively, as previously described with respect to phase-shiftfilter 812 some embodiments of carrier offset post filter 944 are a FIRfilter with a length of 31 samples and having filter tap coefficientsMMSE optimized for a VSB or offset-QAM receiver acquisition SNRthreshold of 15.1 dB. The resultant filter is qualitatively illustratedin FIG. 36B. Other embodiments of carrier offset post filter 944 includefilter tap values optimized for a receiver acquisition SNR threshold ofless than 15.1 dB. At least one embodiment of the carrier trackingfeedback loop includes carrier offset post filter 944 with coefficientsoptimized for an acquisition SNR threshold of 15 dB. In otherembodiments, carrier offset post filter 944 develops a phase errorestimate at an output thereof similar to the phase error estimatedeveloped in the embodiments of phase trackers 800A, 800C, 800D and800E.

Multiplier 948 forms the decision directed carrier tracking feedbacksignal 74A by multiplying the output of carrier offset post filter 944by error feedback signal 942A. It will be understood that one or moredelay elements are used in various embodiments to temporally align theinputs to multiplier 948.

Timing offset post filter 946 filters equalizer output 930B to detect atiming or synchronization offset. In some embodiments, timing offsetpost filter 946 is a correlation filter optimized to detect anarbitrarily small fractional timing offset. In other embodiments, timingoffset post filter 946 combines the output of a timing lead filter and atiming lag filter where the timing lead filter detects positive timingoffsets and the timing lag filter detects negative timing offsets. Otherembodiments of timing offset post filter 946 sum the timing lead andtiming lag filter outputs to produce a symmetrical timing offset errorsignal at the output of timing offset post filter 946. Still otherembodiments of timing offset post filter 946 MMSE-optimize coefficientsfor a FIR filter to produce an impulse response in the presence of whitenoise for a given receiver acquisition threshold. Illustratively, insome embodiments the filter coefficients are developed by a techniquethat includes summing the coefficients of a first filter and secondfilter where the first and second filter coefficients are optimized todetect a lead timing offset and a lag timing offset, respectively. Inother embodiments, developing the coefficients of timing offset postfilter 946 further includes averaging the coefficients of the first andsecond filters.

In certain embodiments, developing the coefficients of timing offsetpost filter 946 includes adding or averaging the coefficients of twofilters. Each filter is MMSE-optimized to produce an impulse responsefor detecting arbitrarily small fractional timing offsets in thepresence of white noise where the SNR is less than or equal to thereceiver acquisition threshold. The coefficients of the two filters areoptimized to detect timing offsets in opposite directions.Illustratively, in some embodiments, the first filter is optimized todetect a 1/10^(th) symbol timing offset (lead) and second filter isoptimized to detect a − 1/10^(th) symbol timing offset (lag), and thefirst and second filter coefficients are asymmetrical. The coefficientsof filter 946 are then obtained by averaging or adding the coefficientsof the first and second filters. The resultant filter is a symmetricalfilter, as qualitatively shown in FIG. 36A, that detects arbitrarilysmall fractional timing offsets in the presence of white noise where theSNR is less than or equal to the receiver acquisition threshold.

Adding or averaging the coefficients of the first and second filtersproduces coefficients of filter 946 that are symmetric and correlateleading and lagging timing offsets. Illustratively, some embodiments offilter 946 are MMSE-optimized to produce an impulse response in thepresence of white noise in a channel having a 15.1 dB SNR. Still otherembodiments of filter 946 produce a maximum correlation for a 1/10^(th)symbol timing offset.

Still other embodiments of timing offset post filter 946 include a FFEwith a length of 31 samples that has filter tap coefficientsMMSE-optimized for a VSB or offset-QAM receiver acquisition SNRthreshold of 15.1 dB. Other embodiments of timing offset post filter 946include filter tap values optimized for a receiver acquisition SNRthreshold of less than 15.1 dB. At least one embodiment of the presentinvention includes timing offset post filter 946 coefficients optimizedfor an acquisition SNR threshold of 15 dB.

Returning to FIG. 29, multiplier 950 multiplies the output of timingoffset post filter 946 by error feedback signal 942A to produce adecision directed synchronization feedback signal 66A that correspondsto a particular received symbol. It will be understood that delayelements are used in some embodiments to temporally align the inputs tomultiplier 950.

Data received by system 900 is provided to A/D 912, which samples thereceived near-baseband signal 60A at a clock rate governed byfeedback-controlled VCXO 914. Digital mixer 922 down modulates thedigitized near-baseband signal 62A from A/D 912 based upon the localcarrier frequency generated by feedback-controlled NCO 924. The outputof digital mixer 922 is filtered (not shown for sake of simplicity) toproduce a digitized baseband signal 920A. In some embodiments, as shownin FIG. 3, a Nyquist filter filters the output of the digital mixer. Itwill be appreciated by those skilled in the art that other filters canbe used to filter the output of digital mixer 922, as well. Returning toFIG. 29, equalizer 930 receives the digitized baseband signal 920A andremoves from it any residual channel distortions and multipathinterference. Some embodiments of equalizer 930 also include a phasetracker to remove residual carrier phase error.

As described below, the operation of synchronization 910 is selectivelygoverned by either non-coherent synchronization feedback signal 64A ordecision directed synchronization feedback signal 66A based upon theoperational state of system 900. Similarly, the operation of digitaldemodulator 920 is selectively governed by either non-coherent carriertracking feedback signal 72A or decision directed carrier trackingfeedback signal 74A based upon the operational state of system 900.

NCC 950 receives the output of digital mixer 922 develops bothnon-coherent synchronization feedback signal 64A and carrier trackingfeedback signal 72A. NCC 950 uses combination the pilot signal andredundant information on the upper and lower Nyquist slopes to developthe non-coherent carrier tracking feedback signal 72A and a non-coherentsynchronization feedback signal 64A in a manner described in co-pendingapplications U.S. application Ser. No. 10/408,053, and U.S. applicationSer. No. 10/407,634, incorporated by reference herein. The developmentof these signals by NCC 950 preferably does not depend upon the outputof equalizer 930.

As previously described, equalizer 930 provides equalizer outputs 930Cand 930D to subtractor 942, which forms the error feedback signals 942A.Equalizer 930 also provides an equalizer output 930A to carrier offsetpost filter 944. Carrier offset post filter 944 filters equalizer output930A to detect carrier frequency or phase errors. Multiplier 948 formsthe decision directed carrier tracking feedback signal 74A bymultiplying the output of carrier tracking filter 944 by error feedbacksignal 942A. Similarly, timing offset post filter 946 filters equalizeroutput 930B to detect timing and synchronization errors, then multiplier950 forms the decision directed feedback synchronization feedback signal66A by multiplying the output of timing offset post filter 946 by errorfeedback signal 942A. As previously discussed, it will be understoodthat delays not shown in FIG. 29 are placed in the various signal pathsto temporally align the various signals so the error feedback signal942A corresponds to the outputs of carrier offset post filter 944 andtiming offset post filter 946, respectively.

The feedback loop that controls digital demodulator 920 is formed byfeeding back the non-coherent carrier tracking feedback signal 72A anddecision directed carrier tracking feedback signal 74A to loop filter926. As described later, depending upon the operational state of system900, control system 954 selectively controls loop filter 926 to useeither non-coherent carrier tracking feedback signal 72A or decisiondirected carrier tracking feedback signal 74A. Loop filter 926 filtersthe selected feedback signal and provides a control signal to NCO 924.NCO 924 provides digital mixer 922 a digital representation of a localcarrier to down modulate the digitized near-baseband signal 62A. In someembodiments, loop filter 926 low-pass filters the selected feedbacksignal. In other embodiments, loop filter 926 integrates the selectedfeedback signal, and then low-pass filters the integrated output.Illustratively, in certain embodiments, the selected feedback signalpasses through a perfect integrator before it is low-pass filtered andprovided to NCO 924. In certain other embodiments, the selected feedbacksignal is passed through a “leaky” integrator before it is low-passfiltered and provided to NCO 924.

Similarly, the feedback loop that controls synchronization 910 is formedby feeding back the non-coherent synchronization feedback signal 64A anddecision directed synchronization feedback signal 66A to loop filter916. As described later, depending upon the operational state of system900, control system 970 selectively controls loop filter 916 to useeither non-coherent synchronization feedback signal 64A or decisiondirected synchronization feedback signal 66A. Loop filter 916 filtersthe selected feedback signal and provides a control signal to VCXO 914.A/D 912 receives a feedback-controlled sampling clock from VCXO 914,which minimizes synchronization-introduced errors in the outputs ofequalizer 930.

Another embodiment of system 900, the operation of which is illustratedin FIG. 30 with continuing reference to system 900 of FIG. 29, comprisesa system 1000 for controlling the operation of the equalizeroptimization process and synchronization and demodulation controlfeedback loops. At 1010, “initial acquire mode,” control system 954initializes system 900. Equalizer 930 is not yet operating. The phasetracker of the equalizer and CDEU are not yet functional or are held ina reset state. The NCC 950 is operational. Control system 954 placessynchronization 910 and digital demodulator 920 in acquisition mode andselectively controls loop filter 916 and loop filter 926 to select thenon-coherent synchronization feedback signal 64A and non-coherentcarrier tracking feedback signal 72A of NCC 950. After some period oftime, control system 954 receives positive assertions from VCXO lock 102and NCO lock 104 that the synchronization 910 and digital demodulator920 are locked to the incoming signal. After both VCXO lock and NCO lockare asserted, control system 954 transitions system 900 operation fromstate 1010 to 1012.

At 1012, “calculate channel delay estimate,” control system 954 turns onthe CDEU portion of equalizer 930. The other portions of equalizer 930remain non-operational. Control system 954 continues to holdsynchronization 910 and digital demodulator 920 in acquisition mode. Thenon-coherent feedback signals of NCC 950 continue to govern thesynchronization and demodulation operations of system 900. Once the CDEUportion of equalizer 930 calculates the channel delay estimate anddetermines the desired timing for the segment sync and frame sync at theoutput of the FFE, control system 954 transitions system 900 operationfrom state 1012 to 1014.

At 1014, “equalizer training with segment sync,” control system 954enables the FFE portion of equalizer 930, and places the DFE portion ofequalizer 930 in IIR mode. In IIR mode, DFE receives sliced data fromthe decision device of equalizer 930. In those embodiments having aphase tracker, the phase tracker is placed in bypass mode. Controlsystem 954 uses the segment sync as a training signal to adapt the FFEcoefficients. After control system 954 receives at least one positiveindication from field/frame sync 98 that field/frame sync was detected,control system 954 transitions system 900 operation from state 1014 to1016. However, in some embodiments, system 900 includes a time-outfeature whereby control system 954 returns the operation of system 900from state 1012 to 1010 when an insufficient number of field/frame syncindications are received to indicate progress toward properly adaptingthe equalizer coefficients.

In some embodiments, segment sync comes from the CDEU of equalizer 930.In other embodiments, where CDEU computes the channel delay estimatebased upon the correlation of the incoming signal with a field/framesync sequence, the frame sync signal comes from the CDEU of equalizer930. Otherwise, a portion of equalizer 930 generates a frame sync basedupon either an intermediate equalized signal of the equalizer or theequalizer output, (similar to intermediate equalized signal 90 orequalizer output 88 of FIG. 5).

At 1016, “equalizer training with segment sync” and field/frame sync,control system 954 develops the coefficients of the FFE portion ofequalizer 930 using both the field/frame sync and segment sync astraining signals. The DFE portion of equalizer 930 continues to operatein IIR mode. Similarly, the phase tracker portion of equalizer 930continues to operate in bypass mode. Control system 954 monitorsfield/frame sync 98 and SNR 100, and transitions system 900 operationfrom state 1016 to 1018 when the measured signal has an estimated SNRgreater than a predetermined RCA_ENB Threshold. However, control system954 instead transitions system 900 operation from state 1016 to 1010 ifit detects the loss of field/frame sync indication.

At 1018, “equalizer training in RCA mode,” control system 954 enablesthe DFE portion of the equalizer of system 900. Control system 954adapts the FFE and DFE coefficients using an RCA-based LMS algorithm onthe received data. In other embodiments, control system 54 furtherincludes a technique of comparing the received synchronization signalsto those generated by control system 54. In still other embodiments,control system 54 weights the effects of the RCA and synchronizationsignal based adaptation techniques depending upon system performance oroperational state. Control system 954 transitions system 900 operationfrom state 1018 to 1020 when the measured signal has an estimated SNRthat exceeds a predetermined Decision Directed Threshold, e.g., 12 dB.If, instead, the estimated SNR drops below a predeterminedReturn_Sync_Training Threshold, e.g., 6 dB, control system 954 passessystem 900 operation from state 1018 to 1016. Similarly, control system954 transitions system 900 operation from state 1018 to 1010 if itdetects the loss of field/frame sync indication.

At 1020, “Decision Directed Mode,” control system 954 adapts the FFE andDFE coefficients using a decision directed LMS technique on the receiveddata and synchronization signals. In addition, control system 954selectively controls loop filter 916 and loop filter 926 to select thedecision directed synchronization feedback signal 66A and decisiondirected carrier tracking feedback signal 74A, respectively. Controlsystem 954 keeps the operation of system 900 at 1020 as long as theestimated SNR remains above a predetermined RETURN_RCA_MODE Threshold,but passes system 900 operation from state 1020 to 1018 if the estimatedSNR drops below the RETURN_RCA_MODE Threshold. Control system 954transitions system 900 operation from state 1020 to 1010 if it detectsthe loss of field/frame sync indication.

Another embodiment of system 900, shown as system 900A in FIG. 31,includes components for interrelating the decision directed phasetracking and carrier tracking feedback loops. System 900A is similar inform and function to equalizer 200A of FIG. 27, which includes phasetracker 800E. It will be understood that other embodiments of system900A use other embodiments of phase tracker 800. System 900A, however,also includes demodulator 920, which receives digitized near-basebandsignal 62A and provides digitized baseband signal 920A as an input toFFE 210. Loop filter 926 receives phase correction signal θ fromintegrator 816, 74B, whereas in system 900 loop filter 926 receivesdecision directed carrier tracking feedback signal 74A (see FIG. 29).

System 900A couples the decision directed carrier tracking feedback anddecision directed phase error signals. The input to integrator 816 is adecision directed phase error signal 843 similar to decision directedcarrier tracking feedback signal 74A. In some embodiments the decisiondirected phase error signal 843 and decision directed carrier trackingfeedback signal 74A are equivalent. Integrator 816 integrates decisiondirected phase error signal 843 at the output of a phase detector 841 toprovide phase correction signal θ (74B). The phase detector 841 may beimplemented in any fashion known to one skilled in the art; for example,any of the approaches illustrated in FIGS. 23-28 may be utilized. Forexample, the phase detector 841 can be implemented by the phase shiftfilter 840 and the multiplier 822 of FIG. 27. Loop filter 926 furtherlow-pass filters phase correction signal θ and provides a control signalto NCO 924. This effectively links the phase tracker feedback andcarrier tracking loops. As a result, rotator 814 corrects for moreinstantaneous phase errors resulting from carrier tracking errors, whiledigital demodulator 920 tracks out the longer term carrier trackingerrors. In addition, the interaction of the phase tracker and digitaldemodulator feedback loops insures that the phase tracker operation doesnot saturate. In addition, it will be understood by those skilled in theart that a similar technique can be combined with the other phasetracker embodiments previously discussed.

In certain other embodiments of system 900, shown as system 900B in FIG.32, the decision directed carrier tracking and phase tracking feedbackloops are interrelated. System 900B is similar in form and function tosystem 900A of FIG. 31, and includes equalizer 200A of FIG. 27 withphase tracker 800E and digital demodulator 920. Digital demodulator 920receives digitized near-baseband signal 62A and provides digitizedbaseband signal 920A as an input to FFE 210. However, the decisiondirected phase error signal 843 from the output of phase detector 841(input of integrator 816) is used as the decision directed carriertracking feedback signal 74B′ instead of phase correction signal θ fromthe output of integrator 816. Loop filter 926 receives and low-passfilters the output of phase detector 841 to provide a control signal toNCO 924. This effectively links the phase tracker feedback and carriertracking loops. As a result, rotator 814 corrects for more instantaneousphase errors resulting from carrier tracking errors, while digitaldemodulator 920 tracks out the longer-term carrier tracking errors. Theinteraction of the phase tracker and digital demodulator feedback loopsallows the carrier tracking feedback loop to compensate for potentialphase tracker saturation. Those skilled in the art will be able to adaptthis technique to other phase tracker embodiments previously discussedwithout undue experimentation.

Yet other embodiments of system 900, illustrated as system 900C of FIG.33, use the outputs of an equalizer decision device to develop a carriertracking feedback signal 74C and a synchronization feedback signal 66C.System 900C is similar in form and function to system 900, except thatdecision directed control (DDC) 940 is replaced with decision directedcontrol 940C. Equalizer 930 provides the equalized output 930E andtrellis decoder output 930F as inputs to DDC 940C.

Decision directed control 940C provides decision directedsynchronization feedback signal 66C to synchronization 910 in place ofdecision directed synchronization feedback signal 66A. Decision directedcontrol 940C provides decision directed carrier tracking feedback signal74C to digital demodulator 920 in place of decision directed carriertracking feedback signal 74A (see FIG. 29).

Decision directed control 940C includes pulse shaping filters 960 and962, conjugate 964, delay line 966, two-symbol clock delay 968,subtractor 970, single-symbol clock delay 972, complex multiplier 974,and complex multiplier 976. Filter 960 receives equalized output 930Eand provides a complex signal output, Y(n+n₀), to delay line 966 whereno is the delay in symbol clocks introduced by the trellis decoder ofequalizer 930 and conjugate 964. Delay line 966 introduces no symbolclocks of delay and provides Y(n) as an output to two-symbol clock delay968, the positive input of subtractor 970, and complex multiplier 976.Two-symbol clock delay 968 introduces an additional two-symbol clock ofdelay and provides Y(n−2) to subtractor 970. Similarly, pulse shapingfilter 962 receives trellis decoder output 930F and provides a complexsignal output, A(n), to conjugate 964. It is understood that in someembodiments the functions of pulse shaping filter 962 and conjugate 964are combined. Conjugate 964 provides A*(n) to single-symbol clock delay972, which provides a one symbol clock delayed output, A*(n−1), as aninput to complex multiplier 974. Conjugate 964 also provides A*(n) tocomplex multiplier 976.

Pulse shaping filter 960 receives the equalizer decision slicer outputthat has not been error corrected. Pulse shaping filter 960 provides acomplex-valued in-phase/quadrature pair representation of the decisionslicer output, Y(n+n₀)=I_(S)(n+n₀)+j Q_(S)(n+n₀). I_(S)(n+n₀) is thedelayed version of the real-valued input to pulse shaping filter 960.Q_(S)(n+n₀) is a 90-degree phase-shifted or quadrature-filtered outputfor the real-valued input to pulse shaping filter 960.

Similarly, pulse shaping filter 962 receives the corrected version ofthe equalizer decision slicer output from a trellis decoder in equalizer930. Pulse shaping filter 962 provides a complex-valuedin-phase/quadrature pair representation of the decision slicer output,A(n)=I_(T)(n)+j Q_(T)(n). I_(T)(n) is the delayed version of thereal-valued input to pulse shaping filter 962. Q_(T)(n) is a 90-degreephase-shifted or quadrature-filtered output for the real-valued input topulse shaping filter 962.

In some embodiments, pulse shaping filters 960 and 962 are each similarto a Hilbert transform filter and include a phase-shift or quadraturefilter to produce the quadrature portions of the complex pairs Q_(S)(n)and Q_(T)(n), and a delay line to provide the real-valued outputsI_(S)(n) and I_(T)(n) respectively. In some embodiments, the phase-shiftor quadrature filter are similar in form and function to the phase-shiftfilter 812 discussed above in relation to FIGS. 23-28.

Delay line 966 compensates for the propagation delay, Z^(n) ⁰ , betweenthe equalized output 930E on one hand and trellis decoder output 930Fand conjugate 964 on the other. Thus, the outputs of delay line 966,Y(n)=I_(S)(n)+j Q_(S)(n), and conjugate 964, A*(n)=I_(T)(n)−j Q_(T)(n),are temporally related to the same decision slicer output. The output ofsubtractor 970 is the difference Y(n)−Y(n−2) and is multiplied by theone symbol clock delayed output of conjugate 964, A*(n−1). This iseffectively the projection of the corrected decision slicer output uponthe previous and next decoded symbols, and represents thesynchronization-related ISI. The real portion of the output ofmultiplier 974, F_(66C), is the decision directed synchronizationfeedback signal 66C provided to loop filter 916:F _(66C) =I _(T)(n−1)·[I _(S)(n)−I _(S)(n−2)]+Q _(T)(n−1)·[Q _(S)(n)−Q_(S)(n−2)]

In some embodiments, loop filter 916 integrates and then low-passfilters decision directed synchronization feedback signal 66C to producea control signal to govern the operation of NCO 924. In otherembodiments, loop filter 916 only low-pass filters decision directedsynchronization feedback signal 66C to produce a control signal togovern the operation of NCO 924.

Similarly, multiplier 976 performs a complex multiply operation. Theimaginary portion of the output of multiplier 976, F_(74C), is adecision directed carrier tracking feedback signal 74C provided onoutput F_(74C)=I_(T)(n)·Q_(S)(n)−Q_(T)(n)·I_(S)(n) to loop filter 926.

In some embodiments, loop filter 926 integrates and then low-passfilters decision directed carrier tracking feedback signal 74C toproduce a control signal that governs the operation of VCXO 914. Inother embodiments, loop filter 926 only low-pass filters decisiondirected carrier tracking feedback signal 74C to produce a controlsignal to govern the operation of VCXO 914.

Yet other embodiments of system 900, illustrated as system 900D of FIG.34, use the outputs of a decision device of an equalizer to developdecision directed synchronization feedback signal 66D. Functionally,system 900D is similar in form and function to system 900, exceptdecision directed control 940 is replaced with decision directed control940D. As shown in FIG. 34, system 900D also produces decision directedsynchronization feedback signal 74C similar to system 900C. However, insystem 900D, delay line 966 provides an output to single-symbol clockdelay 972 whereas in system 900C delay line 966 receives the output ofconjugate 964. Similarly, in system 900D, two-symbol clock delay 968 andthe positive input of subtractor 970 receive the output of conjugate 964whereas in system 900C delay line 966 provides an output to two-symbolclock delay 968 and the positive input of subtractor 970.

Similar to system 900C, pulse shaping filter 960 receives the equalizedoutput 930E that is not error corrected from equalizer 930. Pulseshaping filter 960 provides a complex-valued in-phase/quadrature pairrepresentation of the decision slicer output, Y(n+n₀)=I_(S)(n+n₀)+jQ_(S)(n+n₀). As previously described, I_(S)(n+n₀) is the delayed versionof the real-valued input to pulse shaping filter 960 whereas Q_(S)(n+n₀)is a 90-degree phase-shifted or quadrature-filtered output for thereal-valued input to pulse shaping filter 960. Delay line 966compensates for the delay introduced by the trellis decoder of equalizer930 and conjugate 964 and provides a delayed complex representation ofthe decision device decision slicer output to the inputs ofone-symbol-clock delay 972 and multiplier 976. The output ofone-symbol-clock delay 972 provides an additional symbol clock of delaybetween the output of delay line 966 and the input of multiplier 974.

Pulse shaping filter 962 is similar in form and function to pulseshaping filter 960 and receives the trellis decoder output 930F ofequalizer 930. Pulse shaping filter 962 provides a complexrepresentation of the trellis decoder output to conjugate 964. Conjugate964 provides the conjugate of the received input to multiplier 976,two-symbol clock delay 968, and the positive input of subtractor 970.Two-symbol clock delay 968 provides a two-symbol clock delayed output ofconjugate 964 to the negating input of subtractor 970. Multiplier 974receives the output of subtractor 970. Multiplier 974 performs a complexmultiply of the received inputs and produces the real component at anoutput, F_(66D), as decision directed synchronization feedback signal66D:F_(66D)=I_(S)(n−1)·[I_(T)(n)−I_(T)(n−2)]+Q_(S)(n−1)·[Q_(T)(n)−Q_(T)(n−2)].

Although not shown, similar to system 900C, system 900D providesdecision directed synchronization feedback signal F_(66D) to loop filter916 which integrates and then low-pass filters decision directedsynchronization feedback signal 66D to produce a control signal togovern the operation of VCXO 914. In other embodiments of system 900D,loop filter 916 only low-pass filters decision directed synchronizationfeedback signal 66D to produce a control signal to govern the operationof VCXO 914.

Still another embodiment of system 900, illustrated as system 900E ofFIG. 35 with continuing reference to system 900C of FIG. 33, uses theoutput of equalizer 930 to develop a decision directed synchronizationfeedback signal 66E. Functionally, system 900E is similar in form andfunction to systems 900C and 900D except in the formation of thedecision directed synchronization feedback signal 66E provided to loopfilter 916 shown in FIG. 33. As shown in FIG. 35, system 900E includesequalizer 930, delay line 966, two-symbol clock delay 968, subtractor970, multiplier 974, multiplier 976, four-symbol clock delay 978,two-symbol clock delay 980, four-symbol clock delay 982, subtractor 984,and subtractor 986.

Equalizer 930 provides the equalized output 930E, also referred to asY(n+n_(a)), to delay line 966. Delay line 966 introduces n_(a) symbolclocks of delay to compensate for the delay of the trellis decoder ofequalizer 930. Delay line 966 provides Y(n) as an output to two-symbolclock delay 968, the positive input of subtractor 970 and four-symbolclock delay 978. Four-symbol clock delay 978 introduces an additionalfour-symbol clocks of delay and provides Y(n−4) to the negating input ofsubtractor 970. Subtractor 970 provides the difference signalY(n)−Y(n−4) to multiplier 974.

Trellis decoder output 930F (referred to hereinafter as A(n)) isprovided to two-symbol clock delay 980, four-symbol clock delay 982 andthe positive input of subtractor 984. Four-symbol clock delay 982provides a four clock delayed copy A(n−4) of the trellis decoder output930F to the negating input of subtractor 984.

Multiplier 976 receives Y(n−2) from two-symbol clock delay 968 and adifference A(n)−A(n−4) from subtractor 984. Multiplier 976 provides theproduct Y(n−2)[A(n)−A(n−4)] to the positive input of subtractor 986.Similarly, multiplier 974 receives the difference Y(n)−Y(n−4) fromsubtractor 970 and A(n−2) from two-symbol clock delay 980. Multiplier974 provides the product A(n−2)[Y(n)−Y(n−4)] to the negating input ofsubtractor 986. The output of subtractor 986 develops the decisiondirected synchronization control signalF _(66E) =Y(n−2)[A(n)−A(n−4)]−A(n−2)[Y(n)−Y(n−4)].

In some embodiments, the CDE estimate is calculated one time at thebeginning of each equalizer adaptation process, illustratively, eachtime the receiver is tuned to a different signal source. In otherembodiments, the CDE estimate is recalculated as an ongoing process tofind the optimum virtual center position as channel conditions change.The virtual center is shifted according to the updated virtual centerposition by slowly changing the sampling clock frequency orrepositioning the training signals over a period of time whilemaintaining system integrity.

As illustrated in FIG. 37, another embodiment of system 20 iscorrelation directed control (CDC) 1100. Similar to CDEU 230C of FIG.14, CDC 1100 includes symbol counter 316, segment counter 318,correlators 510 and 512, magnitude calculator 392A, correlation buffer514A, threshold detector 516A, controller 520 and memory 530. CDC 1100further includes centroid weighting function (CWF) 1102, switches 1104,1106, and 1108, filter 1110, and adder 1120.

Although not shown, controller 520 also includes configuration andcontrol interfaces to the elements of CDC 1100. This includes, forexample, reset and enabling signals, the ability to read and writeregisters, and facilities for sending or receiving indications to, from,or between the other elements. Some embodiments of CDC 1100 furtherinclude a centroid estimator similar in form and function to centroidestimator 340A, as previously described in FIG. 14.

Correlation directed control 1100 receives filtered baseband signalsI_(F) 76 and Q_(F) 78 as inputs to correlators 510 and 512,respectively. In some embodiments, CDC 1100 is adapted to receivetwo-times (2×) over-sampled representations of I_(F) and Q_(F). In otherembodiments, CDC 1100 is adapted to receive a symbol rate representationof I_(F) and Q_(F). Still other embodiments of CDC 1100 are adapted toother over-sampled representations of the input signals. Correlators 510and 512 operate on I_(F) and Q_(F) to produce frame sync correlationsignals SCV_(I)(i) and SCV_(Q)(i), which are provided to magnitudecalculator 392A. Similar to magnitude calculator 392, magnitudecalculator 392A calculates MAG_(FS)(i). In some embodimentsMAG_(FS)(i)=|SCV_(I)(i)|+|SCV_(Q)(i)|. In other embodimentsMAG_(FS)(i)=SCV_(I) ²(i)+SCV_(Q) ²(i). The output of magnitudecalculator 392A is frame sync correlation magnitude FSCM(i). In someembodiments, FSCM(i) is MAG_(FS)(i). In other embodiments, magnitudecalculator 392A low pass filters MAG_(FS)(i) to produce FSCM(i).Correlation buffer 514A and threshold detector 516A receive FSCM(i) frommagnitude calculator 392A. Illustratively, some embodiments of magnitudecalculator 392A, receiving a 2× over-sampled representation of I_(F) andQ_(F), include a three-tap FIR filter. This allows the FIR filter tocapture the majority of the power of a single field/frame synccorrelation impulse, regardless of the sampling phase. The number oftaps and filter complexity are based upon the over-sampled rate and needfor noise reduction.

Correlation buffer 514A is scaled to receive the samples produced bymagnitude calculator 392A. Illustratively, in some embodiments,correlation buffer 514A is scaled to receive 2049 values of FSCM(i).Still other embodiments include 1025 FSCM(i) samples. It will beunderstood that some embodiments of correlation buffer 514A are scaledto interface with fractionally spaced samples. Controller 520 interfaceswith memory 530 and receives the values of SC and SEGCNT from symbolcounter 316 and segment counter 318, respectively. As previouslydescribed in the above embodiments, controller 520 also provides channeldelay estimate 84 and is connected to control system 54 (see FIG. 3).

Similar to CDEU 230C of FIG. 14, system 1100 detects the location offrame/field syncs present in the received signals. As described later indetail, threshold detector 516A receives the FSCM(i) values and comparesthem to detection threshold T_(DET), which is the minimum FSCM(i) valuefor detecting a frame sync sequence in the incoming data stream. When aframe sync sequence is detected, controller 520 assigns the values ofWINCENT=i, FSYM=SC, and FSEG=SEGCNT. Controller 520 then calculates thesearch window variables WINSTART and WINEND, which correspond to thefirst and last memory locations of the desired window in correlationbuffer 514A.

Finally, similar to finding the regional G_(MAX), G_(PRE), and G_(POST)as shown in FIG. 17, controller 520 defines regions R₀, R₁, and R₂within the window defined by WINSTART and WINEND. As a non-limitingexample, illustrated in FIG. 38A, P₀, P₁, and P₂ correspond to ghostsignals with the maximum sync correlation value or power in respectiveregions R₀, R₁, and R₂. P₀, P₁, and P₂ are located at indices I₀, I₁,and I₂, respectively. In some embodiments, R₀, R₁, and R₂ span theentire window between WINSTART and WINEND. In other embodiments, as isalso shown in FIG. 38A, R₀, R₁, and R₂ span only a portion of thewindow. As shown in FIG. 38A, the window, W_(FS), spans 2M+1 symboltimes; there are M symbol times preceding and following the symbol timefor P₀. This causes CDC 1100 to select the first maximum-valued FSCM(i)as P₀. Still other embodiments reconfigure threshold detector 516A tolocate FSCM(i)≧P₀. As a result, CDC 1100 selects the last maximum-valuedFSCM(i) within the span of the entire window as P₀.

After locating an initial P₀, controller 520 reconfigures thresholddetector 516A to locate FSCM(i)>P₀. If threshold detector 516A detects aFSCM(i)>P₀, controller 520 re-centers the search window by settingWINCENT=i, FSYM=SC, FSEG=SEGCNT, P₀=FSCM(i), and I_(MAX)=i. Controller520 then recalculates the values of WINSTART and WINEND. This processcontinues until i=WINEND. Controller 520 selects the regions R₀, R₁, andR₂ based upon the final value of WINCENT. Controller 520 then searchescorrelation buffer 514A to find the regional maximums P₁ and P₂ inregions R₁ and R₂, respectively.

Centroid weighting function 1102 receives FSCM(i) from correlationbuffer 514A and calculates a weighted average to drive filter 1110. Insome embodiments, CWF 1102 uses the FSCM(i) values associated with P₀,P₁, and P₂; CWF 1102 then has an output:

${CWF}_{OUT} = {\sum\limits_{{i = I_{0}},I_{1},I_{2}}{{F_{CW}(i)} \cdot {{FSCM}(i)}}}$

In other embodiments, CWF 1102 calculates a weighted average of all thecorrelation values within the regions R₀, R₁, and R₂:

${CWF}_{OUT} = {\sum\limits_{{\forall\;{i \in \; R_{0}}},R_{1},R_{2}}{{F_{CW}(i)} \cdot {{FSCM}(i)}}}$

As shown in FIG. 38B, one embodiment of the windowing function F_(CW)(i)is a set of piecewise linear ramp functions. Other embodiments ofF_(CW)(i), are odd functions defined to have a value of zero outside ofthe regions R₀, R₁, and R₂. Some embodiments have a value of zero inregions R₁ and R₂ as well. As illustrated in FIG. 38C, some embodimentsof CDC 1100 include a F_(CW)(i) based on a windowed sine function.

Centroid weighting function 1102 provides CWF_(OUT) to the first inputof switch 1104. The second input of switch 1104 receives a digital zero.The first and second inputs of switch 1106 receive a digital zero andthe output of switch 1108 (SLEW) respectively. Controller 520 providesthe control signal SLEW ENABLE 1112 to switches 1104 and 1106. AssertingSLEW ENABLE 1112 selects the second inputs of switches 1104 and 1106.This allows controller 520 to control the output of the VCXO byselecting the output of switch 1114. Otherwise, switches 1104 and 1106provide CWF_(OUT) and digital zero to the inputs of filter 1110 andadder 1120 respectively. Switch 1108 receives offset values +F_(OFFSET)1116 and −F_(OFFSET) 1118. In some embodiments, F_(OFFSET) may bedynamically increased by an integrator in controller 520 if it isdetermined that a larger value is required. In other embodiments, thereis a limit on this integrator to keep F_(OFFSET) below a maximum value.Signal SLEW CONTROL 1114, from controller 520, selects the value of SLEWprovided to the second input of switch 1106. Controller 520 slews theVCXO output frequency by selecting either +F_(OFFSET) 1116 or−F_(OFFSET) 1118. Switch 1104 provides an output to filter 1110. Filter1110 and switch 1106 provides inputs to adder 1120, which producesVCXO_(CONTROL) 1140.

In some embodiments filter 1110 is a low pass filter. Illustratively,some embodiments of filter 1110 are configured as a lead-lag filter. Asshown in FIG. 37, filter 1110 includes scalars 1122, 1124, and 1126,adders 1128 and 1130, and delay element 1132. Scalars 1122 and 1124 bothreceive the output of switch 1104 as an input. Scalar 1122 multipliesthe received input by a scalar value C₁ and provides an output to adder1130. Delay element 1132 receives the output of adder 1130 and provides(F_(LOW)) to adder 1130. F_(LOW) represents the low-frequency componentof the VCXO frequency offset relative to the received signal time base.In some embodiments, F_(LOW) is updated each field/frame sync period. Inother embodiments, described later, F_(LOW) is updated each segment syncperiod. Scalar 1124 multiplies output of switch 1104 by a scalar valueC₂ Adder 1128 receives the outputs of scalar 1124 and adder 1130. Scalar1126 multiplies the output of adder 1128 by scalar value C₃ and providesan output to adder 1120.

As illustrated in FIG. 37, switches 1104 and 1106 form a double-poledouble-throw configuration selectively controlled by controller 520signal SLEW ENABLE 1112. When SLEW ENABLE signal 1112 is not asserted,filter 1110 receives CWF_(OUT), and the filter transfer function isH(z)=C₃[C₁(1+Z⁻¹)+C₂]. Thus,VCXO _(CONTROL) =C ₃[(C ₁ +C ₂)CWF _(OUT) +F _(LOW)],where F_(LOW) is the low frequency VCXO offset of the system stored indelay element 1132.

When SLEW ENABLE signal 1112 is enabled, the output of adder 1120 isVCXO _(CONTROL) =C ₃ F _(LOW)+SLEWwhere SLEW is equal to either +F_(OFFSET) or −F_(OFFSET) The output ofdelay element 1132, F_(LOW), remains constant while SLEW ENABLE signal1112 is asserted. This preserves the low frequency offset informationuntil SLEW ENABLE 1112 is de-asserted.

As illustrated in FIG. 39, one embodiment of system 20, includingcorrelation directed synchronization control loop 1150, hassynchronization 910A, demodulator 920 and correlation directed control(CDC) 1100. Synchronization 910A is similar to synchronization 910 ofsystem 900 as previously described in the above embodiments; however,synchronization 910A includes loop filter 916A instead of loop filter916.

Some embodiments of a correlation directed synchronization control loop1150, as shown in FIG. 39, include a CDC 1100 that receives both I_(F)and Q_(F) while other embodiments, similar to CDEU 230A of FIG. 6 or CDC1250 of FIG. 41, only receive I_(F). Returning back to FIG. 39, loopfilter 916A has three feedback inputs. Similar to loop filter 916, loopfilter 916A receives non-coherent synchronization feedback signal 64 anddecision directed synchronization feedback signal 66. Loop filter 916Afurther includes an interface for receiving VCXO_(CONTROL) from CDC1100. Loop filter 916A also includes devices and techniques forswitching between the various feedback control signals provided toinputs thereof. Some embodiments of loop filter 916A also include atechnique for weighting the received feedback control signals.Illustratively, some embodiments of loop filter 916A employ a weightedaverage to transition between decision directed synchronization feedbacksignal 66 and VCXO_(CONTROL) based upon the operational state of system20.

As illustrated in FIG. 39, synchronization 910A receives analog nearbaseband signal 60 and provides demodulator and Nyquist filter block 920with a digitized near baseband signal 62. Demodulator and Nyquist filterblock 920 provides I_(F) 76 to CDC 1100. In some embodiments demodulator920 also provides Q_(F) 78 to CDC 1100.

CDC 1100 produces VCXO_(CONTROL) as an input to loop filter 916A. Loopfilter 916A filters the received control signal and provides a controlsignal to VCXO 914. The A/D 912 receives the clock produced by VCXO 914and samples the received analog near baseband signal 60. Someembodiments of system 20 rely exclusively on CDC 1100 to provide acontrol feedback signal to synchronization 910A. Similarly otherembodiments of system 20 may include some sub-combination ofnon-coherent synchronization feedback control signal 64, decisiondirected feedback signal 66, and the correlation directed control signalVCXO_(CONTROL).

Another embodiment of CDC 1100 adapted for an ATSC broadcast, theoperation of which is implemented by system 1200 of FIG. 40, will now bediscussed with continuing reference to the elements of FIGS. 37 and 39.At 1202 of FIG. 40, “Initialization,” the elements of CDC 1100 areinitialized as will be understood by those skilled in the art.Illustratively, controller 520 resets the elements of CDC 1100;initializes the registers in memory 530, symbol counter 316, segmentcounter 318, magnitude calculator 392A, correlator 510, correlator 512,correlation buffer 514A, CWF 1102, and filter 1110; and configuresvarious control signals shown and not shown. For example, the registercontaining the value of P₀ is set to T_(DET). Furthermore, SC, SEGCNT,and index variable i are initialized. System 1200 then proceeds to 1204.

At 1204, “Correlation,” correlators 510 and 512 receive the most recentfiltered in-phase and quadrature baseband signals I_(F) 76 and Q_(F) 78,respectively. Similar to CDEU 230C of FIG. 14 correlators 510 and 512correlate I_(F) 76 and Q_(F) 78 with a frame sync sequence. As in theembodiments discussed above, magnitude calculator 392A receivesSCV_(I)(i) and SCV_(Q)(i) from correlators 510 and 512, respectively,and calculates the magnitude of the correlation, MAG_(FS)(i). Magnitudecalculator 392A low pass filters MAG_(FS)(i) to produce FSCM(i), whichis provided to correlation buffer 514A and threshold detector 516A.Correlation buffer 514A stores FSCM(i) in array M(i). As discussedabove, some embodiments of magnitude calculator do not include a lowpass filter function; FSCM(i)=MAG_(FS)(i). System 1200 proceeds to 1206.

At 1206, “Detect Frame Sync,” if FSCM(i)<T_(DET) and FSCM(i)<P₀ (anegative result), threshold detector 516A sends a negative indication tocontroller 520 that no frame sync or maximum valued ghost signal wasdetected. Controller 520 then branches system 1200 to 1212. Otherwise,if FSCM(i)≧T_(DET) and FSCM(i)≧P₀ (a positive result at 1206), thresholddetector 516 sends a positive indication to controller 520 that a validmaximum valued ghost signal was detected. Recalling that initiallyP₀=T_(DET), the first indication is the first detected field/frame sync.Subsequently setting P₀=FSCM(I₀) causes system 1200 to detect a maximumframe sync correlation since now P₀≧T_(DET). System 1200 operation thenbranches to 1208.

At 1208, “Store Center,” controller 520 sets FSYM=SC and FSEG=SEGCNT,which saves the temporal location of the maximum frame sync correlationdetected within the data packet field/frame structure. Controller 520also sets WINCENT=i and calculates the search window variables WINSTARTand WINEND, which correspond to the first and last memory locations ofthe desired window in correlation buffer 514A. Finally, controller 520stores I₀=i and P₀=FSCM(I₀). Controller 520 then branches system 1200operation to 1212.

At 1212, “Continue,” controller 520 determines whether to continue to1216 “Find Regional Maximums.” If system 1200 has not previouslydetected a field/frame sync or i≠WINEND, (NO), system 1200 branches to1214. Otherwise, if system 1200 has detected a field/frame sync andi=WINEND, (YES), controller 520 branches system 1200 operation to 1216.

At 1214, “Increment,” the values of symbol counter 316 and segmentcounter 318 are updated. Index variable i is also incremented. System1200 operation continues to 1204.

At 1216, “Find Regional Maximums,” controller 520 defines the regionsR₀, R₁, and R₂. Controller 520 then searches regions R₁ and R₂ to locateP₁ and P₂, respectively. As described above, in some embodiments, CDC1100 also estimates the channel delay based upon the same field/framesync correlation results. System 1200 continues to 1218.

At 1218, “P₀>4P₁,” if P₀>4P₁, system 1200 continues to 1222. Otherwise,system 1200 continues to 1220.

At 1220, “Select New P₀,” controller 520 selects P₁ as the new P₀. Thismay result in P₀ not corresponding to the ghost with the maximum framesync sequence. Following the selection of a new P₀, controller 520redefines the regions R₀, R₁, and R₂. Controller 520 then searchesregions R₁ and R₂ to relocate P₁ and P₂, respectively. Finally, system1200 continues to 1222.

At 1222, “P₀>P₂/9,” if P₀>P₂/9, system 1200 enters a VXCO slew controlloop by continuing to 1224. Otherwise, system 1200 continues to 1230.

At 1224, “−F_(OFFSET),” controller 520 asserts slew enable signal 1212.This causes the output of adder 1120 to provideVCXO_(CONTROL)=C₃·F_(LOW)−F_(OFFSET). As a result, the VCXO clocksampling the received data signal decreases in frequency. Thiseffectively moves the ghost P₂ towards the R₀ region. The VCXO long termfrequency offset from the transmitter symbol time base, F_(LOW), ispreserved in delay element 1132 and represented by C₃·F_(LOW). However,the training signals (Frame Sync and Segment Sync) used to evolve theequalizer coefficients retain the same timing based on the previouslycalculated channel delay. As a result, the virtual center migratestemporally relative to the ghost appearing in the channel withoutrequiring re-initialization of the equalizer structure or re-calculationof the channel delay estimate. System 1200 then proceeds to 1226.

Thereafter, at 1226, “Update Correlation,” when SEGCNT=FSEG, systemcontroller configures CDC 1100 to develop new values of FSCM(i) withinthe window W_(FS) defined by WINSTART, WINEND, FSYM, and FSEG. Thecorrelation values FSCM(i) are updated on a frame or field sync rate. Asillustrated in FIG. 38A, window W_(FS), with 2m+1 samples, begins msymbol times prior to SC=FSYM and SEGCNT=FSEG. Typically window W_(FS)is based upon the first FSCM(i) value detected above threshold T_(DET)by CDC 1100. Thus, subsequent correlation updates may cause P₀ not to becentered within W_(FS). Other embodiments allow W_(FS) to migrate overtime to insure P₀ is, on average, centered within W_(FS). Still otherembodiments recenter W_(FS) as the relative position of P₀ moves overtime. After the updated FSCM(i) values are placed in correlation buffer514A, controller 520 locates the new positions of P₀, P₁, and P₂ in thepreviously defined regions R₀, R₁, and R₂. System 1200 then proceeds to1228.

At 1228, “P₀>P₂/2,” if P₀≦P₂/2 (a negative result), system 1200continues to 1224. This forms a control loop to incrementally adjust theVCXO timing and move P₂ towards region R₀. Once P₀>P₂/2 (positiveresult), system 1200 departs the loop and control proceeds to 1230.

At 1230, “P₀>2P₁,” if P₀>2P₁ system 1200 proceeds to 1238. Otherwise, ifP₀≦2P₁, system 1200 enters the VCXO slew control mode by proceeding to1232.

At 1232, “+F_(OFFSET),” VCXO_(CONTROL)=C₃·F_(LOW)+F_(OFFSET). The VCXOclock frequency increases and temporally reduces the delay of the signalproducing correlation P₁. This causes P₁ to move towards the R₀ region.Similar to before, delay element 1132 retains the value of F_(LOW), andC₃·F_(LOW) preserves the VCXO low frequency offset from the transmittertime base. However, the timing of training pulses (Frame Sync/SegmentSync) used to evolve the equalizer coefficients remains the same. As aresult, the virtual center migrates temporally relative to the ghostappearing in the channel without requiring re-initialization of theequalizer structure or re-calculation of the channel delay.

Then at 1234, “Update Correlation,” controller 520 configures CDC 1100to develop new values of FSCM(i) similar to “Update Correlation” 1236.Controller 520 searches correlation buffer 514A to locate P₀, P₁, and P₂in W_(FS).

At 1236, “P₀>3P₁,” if P₀≦3P₁ (a negative result), system 1200 continuesto 1232. This forms a loop to incrementally adjust the VCXO timing andmoves P₁ towards region R₀. However, once P₀>3P₁ (a positive result at1236), system 1200 departs from the loop and returns to 1222.

At 1238, “CWF_(OUT)” controller 520 de-asserts SLEW ENABLE, andVCXO_(CONTROL)=C₃ [(C₁+C₂) CWF_(OUT)+F_(LOW)].

At 1240, “Update Correlation,” system 1100 develops new values ofFSCM(i) corresponding to the window W_(FS). Controller 520 searchescorrelation buffer 514A to update P₀, P₁, and P₂ as found in R₀, R₁, andR₂. Delay element 1132 updates F_(LOW)=CWF_(OUT) C₁+F_(LOW). System 1200then returns to 1222. In some embodiments, one or more of decisionblocks 1212, 1218, 1222, 1228, 1230, and 1236 may have some type ofconfidence counter that is used to condition the decision transitions.

Another embodiment of system 20 adapted for an ATSC standard broadcast,illustrated as CDC 1250 in FIG. 41, includes CDEU 230A, centroidweighting function 1102, switches 1104, 1106, and 1108, filter 1110,adder 1120, and correlation filter 1134.

Similar to CDEU 230A of FIG. 6, system 1250 receives filtered basebandsignals I_(F) 76 as an input to correlator 310. Although not shown, someembodiments of system 1250 are similar to CDEU 230B and, as explainedabove, calculate the magnitude of the correlation of I_(F) 76 and Q_(F)78 with a segment sync sequence. In some embodiments, similar to CDC1100, system 1250 receives a 2× over-sampled representation of I_(F) andQ_(F). In other embodiments, system 1250 is adapted to receive a symbolrate representation of I_(F) and Q_(F). Still other embodiments ofsystem 1250 include another over-sampled representation of I_(F) 76 andQ_(F) 78.

As illustrated in FIG. 41, correlator 310 operates on I_(F) 76 toproduce symbol correlation value SCV(i). Integrator 312 receives SCV(i)and produces INT(i), which is stored in memory location M(i) ofcorrelation buffer 314. However, as explained later, whereas theprevious described embodiments of CDEU 230A calculate the symbol synccorrelation over N segment sync periods to develop a channel delayestimate, system 1250 continues to update the correlation values,I_(T)(i), stored in correlation buffer 314. This permits continuousupdates to the correlation directed control signal 1252, which isotherwise referred to hereinafter as the VCXO_(CONTROL) signal 1252.Correlation filter 1134 low pass filters the values of INT(i) receivedfrom correlation buffer 314. Some embodiments of system 1250, similar toCDEU 230B of FIG. 13, calculate MAG(i) prior to the low pass filteringoperation. Illustratively, in some embodiments MAG(i)=|INT(i)|. Inembodiments of system 1250, MAG(i)=INT(i)². In embodiments where bothI_(F) 76 and Q_(F) 78 are both processed,MAG(i)=|INT_(I)(i)|+|INT_(Q)(i)| or MAG(i)=[INT_(I)(i)²+INT_(Q)(i)²].Still other embodiments of 1250, not shown, do not include correlationfilter 1134 and rely upon integrator 314 to provide the necessarytemporal filtering.

Centroid Weighting Function 1102 is scaled to receive the appropriatenumber of samples produced by correlation filter 1134. Illustratively,in some embodiments, centroid weighting function 1102 is scaled toreceive 1664 samples. Still other embodiments include 832 samples.Controller 320 interfaces with memory 330 and receives the values of SCand SEGCNT from symbol counter 316 and segment counter 318,respectively. Similar to controller 320 of FIG. 6, controller 320interfaces with control system 54 (see FIG. 3). Controller 320 furtherincludes, although not shown, interfaces to the elements of system 1250necessary for configuration and control.

Similar to CDEU 230A of FIG. 6, system 1250 detects the location ofsegment syncs present in the received signals and determines the CIRestimate. The channel delay is estimated from the CIR estimate and isused to position the virtual center of the overlapped equalizer. Similarto controller 520 of CDC 1100 in FIG. 37, controller 320 searchescorrelation buffer 314 to locate P₀, which corresponds to the maximumvalue of MAG(i). Controller 320 centers region R₀ about P₀. Controller320 then searches correlation buffer 314 to find the local maximumvalues of MAG(i) in regions R₁ and R₂, P₁ and P₂, respectively. As shownin FIG. 38A, P₀, P₁, and P₂ are defined as ghost signals with themaximum correlation value or power in the respective regions R₀, R₁, andR₂. P₀, P₁, and P₂ are located at I₀, I₁, and I₂, respectively. In someembodiments, R₀, R₁, and R₂ span the entire segment sync period. Inother embodiments, R₀, R₁, and R₂ span only a portion of the segmentsync period.

Correlation filter 1134 low pass filters the MAG(i) values provided toCWF 1102. In some embodiments, CWF 1102 only uses the values of P₀, P₁,and P₂; CWF 1102 has an output:

${CWF}_{OUT} = {\sum\limits_{{i = I_{0}},I_{1},I_{2}}{{F_{CW}(i)} \cdot {{MAG}(i)}}}$

In other embodiments, CWF 1102 calculates a weighted average of all theghosts within the regions R₀, R₁, and R₂:

${CWF}_{OUT} = {\sum\limits_{{\forall{i \in R_{0}}},R_{1},R_{2}}{{F_{CW}(i)} \cdot {{MAG}(i)}}}$

Similar to CDC 1100 of FIG. 37, some embodiments CDC 1250 have awindowing function F_(CW)(i) similar to the piecewise linear rampfunctions of FIG. 38B adapted to the appropriate sampling rate. Otherembodiments of F_(CW)(i) are odd functions defined to have a value ofzero outside of the regions R₀, R₁, and R₂. Some embodiments of CDC 1250include a F_(CW)(i) based on a windowed sine function, also adapted tothe sampling rate, similar to FIG. 38C.

Otherwise, system 1250 operates substantially similar to CDC 1100 tocreate correlation directed control signal VCXO_(CONTROL) 1252 at theoutput of adder 1120. Centroid weighting function 1102 provides anoutput thereof as a first input of switch 1104. The second input ofswitch 1104 is a digital zero. The first input to switch 1106 is adigital zero. The second input of switch 1106 is the signal SLEW fromswitch 1108. Switch 1108 receives offset values +F_(OFFSET) 1116 and−F_(OFFSET) 1118. Similar to controller 520 of CDC 1100, controller 320provides SLEW CONTROL signal 1114 to switch 1108 and, as describedlater, slews the output of correlation directed control signal 125 byselecting either +F_(OFFSET) 1116 or −F_(OFFSET) 1118. Switch 1104provides an output to filter 1110. Filter 1110 and switch 1106 provideinputs to adder 1120. The output of adder 1120 is correlation directedcontrol signal VCXO_(CONTROL) 1252.

Similar to CDC 1100 of FIG. 37, switches 1104 and 1106 form adouble-pole double-throw configuration. When controller 320 does notassert SLEW ENABLE 1112, the output of adder 1120 is VCXO_(CONTROL)=C₃[(C₁+C₂) CWF_(OUT)+F_(LOW)], where F_(LOW) is the low frequency offsetof the system stored in delay element 1132. The transfer function offilter 1110 is H(z)=C₃[C₁(1+Z⁻¹)+C₂].

When SLEW ENABLE signal 1112 is enabled, the output of adder 1120 isVCXO_(CONTROL)=C₃·F_(LOW)+SLEW, where SLEW is either +F_(OFFSET) or−F_(OFFSET). The output of delay element 1132, F_(LOW), remains constantwhile SLEW ENABLE signal 1112 is asserted. This preserves the lowfrequency offset information until signal 1112 is de-asserted, therebyre-enabling normal operation of filter 1110. In some embodiments,F_(OFFSET) may be dynamically increased by an integrator in controller520 if it is determined that a larger value is required. In otherembodiments, there is a limit on this integrator to keep F_(OFFSET)below a maximum value.

Another embodiment of system 1250 will now be discussed with continuingreference to elements of FIG. 41, is illustrated as system 1300, theoperation of which is illustrated in FIG. 42, which is also adapted foran ATSC broadcast and symbol sampling rate. At 1302, “Initialization,”controller 320 initializes elements of system 1250. Illustratively,controller 320 initializes the registers in memory 330, symbol counter316, segment counter 318, magnitude calculator 392, correlator 310,correlation buffer 314, CWF 1102, filter 1110, correlation filter 1134,and various control signals. Furthermore, SC, SEGCNT, and index variablei are initialized. After initialization of system 1300, operationproceeds to 1304.

At 1304, “SCV,” similar to system 400 of FIG. 12, correlator 310receives a new symbol time of data from filtered in-phase basebandsignal I_(F) 76 and calculates the value of SCV(i) corresponding to thesymbol count produced by symbol counter 316. System 1304 transitions to1306.

At 1306, “Integration,” similar to CDEU 230A integrator 312 receivesSCV(i) from correlator 310 and calculates the value of INT(i) to bestored in array M(i) of correlation buffer 314. System 1300 thenproceeds to 1308.

At 1308, “SC=831,” similar to 410 of system 400 of FIG. 12, controller320 determines whether SC equals the maximum output of symbol counter316. Illustratively, a positive result occurs when SC=831, where SC hasa range of 0 to 831, and system 1300 transitions to 1312. Otherwise, anegative result occurs at 1308, thereby causing system 1300 totransition to 1310 so that symbol counter 316 increments the value of SCand controller 320 increments the index variable i. Control then returnsto 1304.

At 1312, “SEGCNT<N,” controller 320 compares the output of segmentcounter 318, SEGCNT, to the value N stored in segment count register338. If SEGCNT<N, controller 320 branches system 1300 operation to 1314,symbol counter 316 sets SC=0, and segment counter 318 increments SEGCNT.However, if SEGCNT=N, system 1300 operation transitions to 1316.

At 1316, similar to 1216 of system 1200 of FIG. 40, “Find RegionalMaximums,” controller 320 defines the regions R₀, R₁, and R₂. Controller320 then searches regions R₁ and R₂ to locate P₁ and P₂, respectively.In some embodiments, controller 320 inter-operates with a centroidestimator, shown as centroid estimator 340 in FIG. 41, to determine theappropriate CDE value. System 1300 continues to 1318.

At 1318, “P₀>4P₁,” if P₀>4P₁, system 1300 continues to 1322. Otherwise,system 1300 continues to 1320.

At 1320, “Select New P₀,” similar to 1220 of system 1200 of FIG. 40,controller 320 selects P₁ as the new P₀. In some cases, this results inP₀ not corresponding to the maximum value of MAG(i) in correlationbuffer 314. Following this selection, controller 320 redefines theregions R₀, R₁, and R₂ based upon the location of the new P₀. Controller320 then searches regions R₁ and R₂ to locate P₁ and P₂, respectively.Finally, system 1300 continues to 1324.

At 1322, “P₀>P₂/9,” similar to system 1200 of FIG. 40, a negative resultoccurs when P₀≦P₂/9, and system 1300 enters a VXCO slew control loop bycontinuing to 1322. Otherwise, a positive result occurs when P₀>P₂/9,and system 1300 continues to 1330.

At 1324, “−F_(OFFSET),” similar to 1224 of system 1200 of FIG. 40,controller 320 asserts signal SLEW ENABLE 1112. This causes the outputof adder 1120 to provide VCXO_(CONTROL)=C₃·F_(LOW)−F_(OFFSET). Thus,similar to CDC 1100, delay element 1132 preserves the low frequencyoffset F_(LOW) of filter 1110.

At 1326, “Update Correlation,” system 1300 updates the correlationvalues stored in correlation buffer 314. In some embodiments, system1250 integrates SCV(i) values generated during the most recent segmentsync period. In other embodiments, system 1250 re-initializes portionsof 230A and develops a new set of INT(i) and MAG(i) values over a numberof segment sync periods. Controller 320 searches correlation buffer 314to locate updated P₀, P₁, and P₂ falling within the window created bythe existing R₀, R₁, and R₂. Correlation filter 1134 receives theupdated correlation buffer 314 output and provides the updated low passfiltered MAG(i) to CWF 1102. CWF 1102 then calculates an updatedCWF_(OUT). As discussed previously, some embodiments of system 1250 onlyuse the updated P₀, P₁, and P₂ to generate an updated CWF_(OUT).However, similar to CDC 1100, some embodiments of system 1250 migrateregions R₀, R₁, and R₂ in response to a change in location of P₀.

At 1328, “P₀>P₂/2,” a negative result occurs when P₀≦P₂/2, and system1300 remains in the VXCO slew control loop by returning to 1324. Thisforms a loop to incrementally adjust VCXO_(CONTROL). A positive resultoccurs when P₀>P₂/2: system 1300 departs from the VCXO slew controlloop; and system 1300 eventually continues to 1330.

At 1330, “P₀>2P₁,” a positive result occurs when P₀>2P₁, and system 1300proceeds to 1338. Otherwise, a negative result occurs when P₀≦2P₁, andsystem 1300 enters a VCXO slew control loop by proceeding to 1332.

At 1332, “+F_(OFFSET),” similar to system 1200, control 320 assertssignal SLEW ENABLE 1112 and selects SLEW=+F_(OFFSET). Similar to system1100, the output 1252 of adder 1120 becomesVCXO_(CONTROL)=C₃·F_(LOW)+F_(OFFSET), where delay element 1132 preservesthe low frequency offset F_(LOW) of filter 1110.

Then at 1334, “Update Correlation,” system 1300 updates the correlationvalues stored in correlation buffer 314, similar to the previouslydiscussed operation of 1326. The values of INT(i) generated during themost recent segment sync period are updated. Controller 320 searchescorrelation buffer 314 to locate updated P₀, P₁, and P₂ falling withinthe search window created by the existing R₀, R₁, and R₂. As illustratedin FIG. 41, correlation filter 1134 receives the updated correlationbuffer 314 output and provides the updated low pass filtered INT(i) toCWF 1102. CWF 1102 then calculates an updated CWF_(OUT). System 1300proceeds to 1336.

At 1336, “P₀>3P₁,” a negative result occurs when P₀≦3P₁, and system 1300continues in the VCXO slew control loop by returning to 1332. This formsa loop to incrementally adjust VCXO_(CONTROL). A positive result occursat 1336 when P₀>3P₁, and hence system 1300 departs from the VCXO slewcontrol loop and system 1300 returns to 1322.

At 1338, “CWF_(OUT),” after a positive result at 1330, controller 320sets slew control signal 1112 to pass CWF_(OUT) through switch 1104 andzero through switch 1106. CWF_(OUT) is passed through filter 1110. Adder1130 forms the output VCXO_(CONTROL)=C₃ [(C₁+C₂) CWF_(OUT)+F_(LOW)]where, as previously discussed, F_(LOW) is the value stored in delayelement 1132. System 1338 then proceeds to 1340.

At 1340, “Update Correlation,” system 1250 updates the correlationvalues stored in correlation buffer 314 as previously described.Controller 320 searches correlation buffer 314 for updated values of P₀,P₁, and P₂ in the previously defined regions R₀, R₁, and R₂. Delayelement 1132 updates F_(LOW)=CWF_(OUT) C₁+F_(LOW). System 1300 thenreturns to 1322. In some embodiments, one or more of decision blocks1312, 1318, 1322, 1328, 1330, and 1336 may have some type of confidencecounter that is used to condition the decision transitions.

As illustrated in FIG. 43, yet another embodiment of system 20 includesa correlation directed carrier tracking system 1350. Correlationdirected carrier tracking system 1350 includes demodulator 920A andcorrelation directed control 1250A. The demodulator 920A is similar inform and function to demodulator 920 of system 900; however, loop filter926 is replaced by loop filter 926A. As will be explained later, loopfilter 926A further includes a third feedback control input 1252A forreceiving a correlation directed tracking signal. Correlation directedcontrol 1250A is similar in form and function to correlation directedcontrol 1250; however, similar to CDEU 230B of FIG. 13, CDC 1250A isadapted to correlate both I_(F) 76 and Q_(F) 78 with a segment syncsequence.

Demodulator 920A receives digitized near baseband signal 62 and providesthe signals I_(F) 76 and Q_(F) 78 as outputs to CDC 1250A. Demodulator920A also receives non-coherent carrier tracking feedback signal 72 anddecision directed carrier tracking feedback signal 74. In addition, thedemodulator 920A further receives correlation directed carrier trackingsignal 1252A from CDC 1250A.

As illustrated in FIG. 44, another embodiment of system 20 includes achannel delay directed control system 1360, which includessynchronization 910, demodulator 920, CDEU 230E, subtractor 1360, anddelay 1362.

The CIR directed control system 1360 receives an analog near basebandsignal 60 at synchronization 910. Synchronization 920 digitizes theanalog near baseband signal 60, and provides a digitized near basebandsignal 62 to demodulator 920. Demodulator 390 demodulates the digitizednear baseband signal 62, and provides I_(F) 76 and Q_(F) 78 as inputs toCDEU 230E. CDEU 230E operates on I_(F) 76 and Q_(F) 78 to calculate anupdated channel delay estimate, CDE_(NEW). CDEU 230E then providesCDE_(NEW) as an input to delay 1362 and the positive input of subtractor1360. Delay 1362 provides the previously calculated value of channeldelay estimate, CDE_(PREVIOUS), as an output to the negating input ofsubtractor 1360. Synchronization 40 receives synchronization controlsignal 1364 from subtractor 1360.

Similar to previous embodiments of CDEU 230, CDEU 230E estimates thechannel impulse response of a transmission channel by detecting thecorrelation strength and delay of the ghost signals received at theinput of CDEU 230E. Some embodiments of CDEU 230E are similar in formand in function to the previously described embodiments of CDEU 230.Illustratively, some embodiments of CDEU 230E are adapted to estimatethe channel delay in an ATSC broadcast system by detecting thecorrelation strength of received ghost signal frame sync sequence,PN511. Likewise, other embodiments of CDEU 230E are similar toembodiments of CDEU 230 that estimate the channel delay based upon thecorrelation of the segment sync. However, CDEU 230E is adapted toprovide continuously updated channel delay estimates. Illustratively,while some embodiments of CDEU 230 provide a single channel delayestimate, used to set up and adapt an overlapped equalizer, embodimentsof CDEU 230E provide continuous channel delay estimate updates. Someembodiments of CDEU 230E provide an updated channel delay estimate everyframe or field sync period. Other embodiments, which estimate thechannel delay based on the receipt of segment sync sequences, provide anupdated channel delay estimate after a desired number of segment syncperiods. In addition, still other embodiments provide an updated channeldelay estimate every segment sync period.

In some embodiments delay 1362 is a latch or register used to store thepreviously calculated channel delay estimate provided by CDEU 230E.Subtractor 1360 produces synchronization control signal 1364 bysubtracting CDE_(PREVIOUS) from CDE_(NEW). The synchronization controlsignal 1364 represents a change of the channel delay estimate due tomovement in the virtual center. Synchronization 910 receivessynchronization control signal 1364 and controls the clock frequencyused to sample the analog near baseband signal 60. This adjusts therelative delay introduced in the equalizer of system 20, and compensatesfor movement in the virtual center.

It will be understood that the lengths of the quadrature and transformfilter implementations are optimized for the total feedback loopresponse. Illustratively, in embodiments where the transform filterperforming the 90-degree rotation is a Hilbert filter that operates onthe received in-phase signal, the length of the Hilbert filter will beadjusted to optimize the phase tracker loop response. Similarly, theresolution of the Hilbert transform can be optimized for hardwarecomplexity and necessary accuracy. Likewise, the phase error integrator812 can be optimized to balance the need for smoother and more accuratephase error information and the phase tracker bandwidth.

Alternatively, in some embodiments having a fractionally-spacedequalizer, the point at which the data is down sampled prior to theequalizer decision device can be moved to provide greater control loopbandwidth. As illustrated in FIG. 29, in some embodiments of system 900the carrier tracking post filter 944 receives fractionally spacedsamples from FFE 210 prior to down sampling. Decision device 212effectively down samples the received data by sampling equalizer outputsignal 88 on a symbol timing basis. In still other embodiments, wherethe fractionally spaced FFE samples are not related by a n:1 integerrelationship, the input to the equalizer decision device is sample rateconverted to the appropriate sample rate. It will be understood thatsome embodiments employ similar techniques to the decision directedphase tracker and decision directed synchronization feedback loops.Additionally, certain embodiments employ a sample rate converter to downsample the output of the fractionally spaced FFE and perform the phasetracker function.

It will be understood that the techniques and devices herein describedcan also be applied to the modulation techniques having anyone-dimensional constellation. Thus, the present invention includesembodiments modified to work with data constellations that have multiplelevels. Similarly, the techniques and devices herein described can beapplied to the modulation of VSB or Offset QAM, for Offset QAMmodulation (where the simple 90-degree phase shift is enough to convertthe Offset QAM baseband complex signal into a VSB baseband like realonly signal).

Still further, any of the systems and/or methods described herein may beapplicable to any broadcast standard. For example, the systems andmethods herein are usable with signals compliant with the ATSC standardsspecified in the following document: “ATSC Digital Television Standard”,ATSC Doc. A/53, Sep. 16, 1995.

Alternatively, by way of example, and not by limitation, any of thesystems and/or methods described herein are/may be usable with signalscompliant with the standards specified in the following document(hereinafter referred to as the “ADTB-T standard”): Zhang, W, et. al.“An Advanced Digital Television Broadcasting System,” Supplement toProceedings 7th International Symposium on Broadcasting Technology,2001.

It will be understood that in some embodiments, the equalizer acts uponin-phase and quadrature data. Similarly, whereas the embodiments andfigures herein show the FFE of the equalizer placed in the basebandregion of receiver, other embodiments of the receiver place the FFE inthe passband, or IF, region. Illustratively, in some embodiments, theFFE of the equalizer is placed between the synchronization anddemodulator components of the system.

Variations in the implementation of the invention will occur to those ofskill in the art. Illustratively, some or all of the generation andcalculation of signals can be performed by application-specific and/orgeneral-purpose integrated circuits, and/or by discrete components,and/or in software. All publications, prior applications, and otherdocuments cited herein are hereby incorporated by reference in theirentirety as if each had been individually incorporated by reference andfully set forth.

While the invention has been illustrated and described in detail in thedrawings and foregoing description, the same is to be considered asillustrative and not restrictive in character, it being understood thatonly the preferred embodiment has been shown and described and that allchanges and modifications that come within the spirit of the inventionare desired to be protected.

We claim:
 1. A method of controlling sampling frequency and samplingphase of a sampling device from a value generated by an equalizercoupled to the sampling device, the method comprising the steps of:generating a complex representation of the value developed by theequalizer; generating a representation of a decision from an output ofthe equalizer; performing delay and multiply operations of the decisionrepresentation with a conjugate of the complex representation to obtaina sampling error estimate; and adjusting the sampling frequency andsampling phase of the sampling device using the sampling error estimate;and wherein the sampling device comprises an analog to digital converterfollowed by a sample rate converter and wherein the step of adjustingincludes the step controlling the sample rate converter to determinesampling instants.
 2. The method of claim 1, wherein the equalizer isadapted to receive ATSC compliant signals.
 3. The method of claim 1,wherein the equalizer is adapted to receive ADTB-T compliant signals. 4.The method of claim 1, wherein the complex representation comprises anin-phase signal and a quadrature signal.
 5. The method of claim 1,wherein the step of generating a representation of a decision isundertaken by a decision device.
 6. The method of claim 5, including thefurther step of transforming a decision representation into a furthercomplex representation.
 7. The method of claim 6, including the furtherstep of forming a conjugate of the further complex representation. 8.The method of claim 5, wherein the decision representation comprises anerror estimate.
 9. The method of claim 5, wherein the decision devicecomprises a decision slicer.
 10. The method of claim 5, wherein thedecision device comprises a trellis decoder.
 11. The method of claim 10,wherein the trellis decoder utilizes a Viterbi algorithm.
 12. The methodof claim 1, wherein the correlating step includes the step of temporallyaligning the decision representation and the complex representation ofthe value developed by the equalizer.
 13. The method of claim 1, whereinthe step of generating a representation is undertaken by a pulse shapingfilter.
 14. The method of claim 13, wherein the pulse shaping filter isa raised cosine filter.
 15. The method of claim 13, wherein the pulseshaping filter includes only a series of delays and adders.
 16. Themethod of claim 1, wherein the step of generating a representation isundertaken by a timing offset post filter.
 17. The method of claim 1,wherein the correlating step is undertaken by a multiplier.
 18. Themethod of claim 1, wherein the sampling device comprises an analog todigital converter having a voltage controlled crystal oscillator (VCXO)and wherein the step of adjusting comprises the step of controlling theVCXO to determine sampling instants.
 19. A decision directed controldevice for controlling sampling frequency and sampling phase of asampling device from a value generated by an equalizer coupled to thesampling device, comprising: first circuitry that generates a complexrepresentation of the value developed by the equalizer; second circuitrythat generates a representation of a decision from an output of theequalizer; third circuitry that performs delay and multiply operationsof the decision representation with a conjugate of the complexrepresentation to obtain sampling error estimate; and fourth circuitrythat adjusts the sampling frequency and sampling phase of the samplingdevice using the sampling error estimate; and wherein the samplingdevice comprises an analog to digital converter followed by a samplerate converter and wherein the step of adjusting includes the stepcontrolling the sample rate converter to determine sampling instants.20. The decision directed control device of claim 19, wherein thecomplex representation comprises an in-phase signal and a quadraturesignal.
 21. The decision directed control device of claim 19, whereinthe circuitry that generates a representation of a decision includes adecision device.
 22. The decision directed control device of claim 21,further including fifth circuitry that transforms the decisionrepresentation into a further complex representation.
 23. The decisiondirected control device of claim 22, further including sixth circuitrythat forms a conjugate of the further complex representation.
 24. Anon-transitory computer-readable medium for controlling samplingfrequency and sampling phase of a sampling device from a value generatedby an equalizer coupled to the sampling device, including programmingfor implementing: a first routine for generating a complexrepresentation of the value developed by the equalizer; a second routinefor generating a representation of a decision from an output of theequalizer; a third routine that performs delay and multiply operationsof the decision representation with a conjugate of the complexrepresentation to obtain a sampling error estimate; and a fourth routinefor adjusting the sampling frequency and sampling phase of the samplingdevice using the sampling error estimate; and wherein the samplingdevice comprises an analog to digital converter followed by a samplerate converter and wherein the step of adjusting includes the stepcontrolling the sample rate converter to determine sampling instants.25. The computer-readable medium of claim 24, wherein the complexrepresentation comprises an in-phase signal and a quadrature signal. 26.The computer-readable medium of claim 24, wherein the second routine isundertaken by a decision device.
 27. The computer-readable medium ofclaim 26, including the further routine of transforming the decisionrepresentation into a further complex representation.
 28. Thecomputer-readable medium of claim 27, including the further routine offorming a conjugate of the further complex representation.